Table of Contents
Related Manuals for United Electronic Industries PD2-MF
Summary of Contents for United Electronic Industries PD2-MF
- Page 1 PowerDAQ User Manual PowerDAQ PD2-MF and PD2-MFS PCI DAQ boards High-Performance Multifunction I/O boards for PCI Bus Computers October 2000 Edition © Copyright 1998-2000 United Electronic Industries, Inc. All rights reserved...
- Page 2 Information furnished in this manual is believed to be accurate and reliable. However, no responsibility is assumed for its use, or for any infringements of patents or other rights of third parties that may result from its use. Contacting United Electronic Industries Address: 10 Dexter Avenue Watertown, Massachusetts 02472 U.S.A.
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Page 3: Table Of Contents
Table of Contents Table of Contents How to Use This Manual..............vi Introduction ..................vi Who Should Read This Book?............vii Organization of This Manual............vii Conventions Used in This Manual ...........viii Feedback ..................viii Introduction ................1 About the PowerDAQ board..............2 Overview .................... - Page 4 Table of Contents Triggering ..................48 Digital Input/Output Subsystem ............49 User Counter-Timer Subsystem............51 PowerDAQ Software Development Kit (PD-SDK) ..53 PowerDAQ Software ................54 PowerDAQ SDK Structure..............54 PowerDAQ Libraries ................. 55 PowerDAQ Include Files..............56 Analog Input Subsystem ..............60 Analog Output Subsystem ..............78 Digital Input/Output Subsystems............86 User Counter-Timer Subsystem............90 PowerDAQ Example Programs ............
- Page 5 Table of Contents Index ....................137...
- Page 6 PowerDAQ block diagram ........... 26 Figure 8: PowerDAQ Multifunction Board front-end ......30 Figure 9: PowerDAQ Sample and Hold Board front-end....31 Figure 10: PD2-MF Series Acquisition Process ........32 Figure 11: PD2-MFS Acquisition Process ..........33 Figure 12: Single-Ended Inputs............. 35 Figure 13: Differential Inputs ...............
- Page 7 Table of Contents List of Tables Table 1: PowerDAQ PD2-MF Models ..........4 Table 2: PowerDAQ PD2-MFS Models ..........5 Table 3: PD2-MFS Differential Upgrade Options........ 6 Table 4: FIFO upgrade options ............7 Table 5: J1 Connector (Single-Ended Mode)........19 Table 6: J1 Connector (Differential Input Mode) ......
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Page 8: How To Use This Manual
How to Use This Manual How to Use This Manual Introduction This manual describes the hardware of each of the PowerDAQ series DAQ boards. The following boards are supported: PowerDAQ PD2-MF Multifunction Series: PD2-MF-16-2M/14H PD2-MF-16-50/16L PD2-MF-64-2M/14H PD2-MF-16-50/16H PD2-MF-16-400/14L PD2-MF-16-333/16L PD2-MF-16-400/14H... -
Page 9: Who Should Read This Book
How to Use This Manual The word PowerDAQ will be used in this manual to reference all the models listed above. Who Should Read This Book? This manual has been designed to benefit the user of PowerDAQ boards. To use PowerDAQ, it is assumed that you have basic PC skills, and that you are familiar with Microsoft Windows 2000/NT/ 9x, QNX or Linux/RTLinux/RTAI Linux operating environments. -
Page 10: Conventions Used In This Manual
How to Use This Manual This appendix contains a detailed explanation of PowerDAQ warranty. Glossary The Glossary contains an alphabetical list and description of terms used in this manual. Index The Index alphabetically lists topics covered in this manual. Conventions Used in This Manual These are the main conventions used to help you get the most out of this manual: Tips are designed to highlight quick ways to get the job... -
Page 11: Introduction
Introduction... -
Page 12: About The Powerdaq Board
Chapter 1: Introduction About the PowerDAQ board This chapter describes the basic features of the PowerDAQ boards. Overview Thank you for purchasing a PowerDAQ board. The PowerDAQ board was designed from the ground-up to overcome the problems associated with previous ISA-based data acquisition boards. The associated PowerDAQ software has been written specifically for these products, using advanced software design. -
Page 13: Powerdaq Models
• Multifunction with sample and hold • Analog Output (requires PD2-AO user manual) • Digital Input/Output (requires PD2-DIO user manual) PowerDAQ PD2-MF Series: Model: Analog features: PD2-MF-16-2M/14H 2.2 MS/s, 14-bit, 16SE/8DI A/D, Gains: 1,2,4,8; Two 12-bit D/A PD2-MF-64-2M/14H 2.2 MS/s, 14-bit, 64SE/32DI A/D, Gains: 1,2,4,8;... -
Page 14: Table 1: Powerdaq Pd2-Mf Models
500 kS/s, 16-bit, 64SE/32DI A/D, Gains: 1,10,100,1000; Two 12-bit D/A PD2-MF-64-500/16H 500 kS/s, 16-bit, 64SE/32DI A/D, Gains: 1,2,4,8; Two 12-bit D/A Table 1: PowerDAQ PD2-MF Models All PowerDAQ PD2 models include 3 counter/timers and 32 Digital I/O lines PowerDAQ PD2-MFS Series:... -
Page 15: Table 2: Powerdaq Pd2-Mfs Models
Chapter 1: Introduction Model: Analog features: PD2-MFS-4-2M/14 2.2 MS/s, 14-bit, 4SE Simultaneous Sample & Hold Two 12-bit D/As PD2-MFS-8-2M/14 2.2 MS/s, 14-bit, 8SE Simultaneous Sample & Hold Two 12-bit D/As PD2-MFS-4-800/14 800 kS/s, 14-bit, 4SE Simultaneous Sample & Hold Two 12-bit D/As PD2-MFS-8-800/14 800 kS/s, 14-bit, 8SE Simultaneous Sample &... -
Page 16: Table 3: Pd2-Mfs Differential Upgrade Options
Chapter 1: Introduction PowerDAQ PD2-MFS differential upgrade with gains: The PD2-MFS series can be upgraded to differential inputs with gains for each channel. One PGA per channel is installed on the board. Upgrade Part Number: Additional features added: PD2-MFS-4-DG4 Upgrade any PD2-MFS board from 4SE to 4DI with Gains (1,2,5,10) PD2-MFS-8-DG8 Upgrade any PD2-MFS board from 8SE to 8DI... -
Page 17: Table 4: Fifo Upgrade Options
Chapter 1: Introduction Upgrade PowerDAQ II board from 1K PD-32KFIFO FIFO to 32K FIFO Upgrade PowerDAQ II board from 1K PD-64KFIFO FIFO to 64K FIFO Table 4: FIFO upgrade options... -
Page 19: Installation And Configuration
Installation and Configuration... -
Page 20: Before You Begin
Chapter 2: Installation and Configuration Before You Begin Before you install your PowerDAQ board, you should read and understand the following information. System Requirements: To install and run your PowerDAQ board, you must have the following: • A PC with PCI slots, a Pentium-class processor, and a PCI Local Bus Specification BIOS that is compliant with Revision 2.1... -
Page 21: Installing Powerdaq
Chapter 2: Installation and Configuration Installing PowerDAQ Installing the Board: To install your PowerDAQ board: Turn off your PC and remove the cover from your PC. 2. Locate an empty PCI slot and remove the slot cover on the back panel of your PC. Save the screw. 3. -
Page 22: Installing The Software
Chapter 2: Installation and Configuration Installing the Software To install the PowerDAQ SDK: Start your PC and, if you are running Windows NT, login as an administrator. 2. Insert the PowerDAQ CD into your CD-ROM drive. Windows should automatically start the PowerDAQ Setup program. If you see the UEI logo and then the PowerDAQ welcome screen, go to step 6. -
Page 23: Confirming The Installation
Chapter 2: Installation and Configuration If the Setup program asks for information about third-party software packages that you do not have installed on your PC, leave the textbox blank and click the Next button. 8. When the installation is complete, you should restart your PC when prompted. -
Page 24: Configuring The Powerdaq Board
Chapter 2: Installation and Configuration Configuring the PowerDAQ Board L o w N o i s e D C - D C D S P L o g i c C o n t r o l L o g i c P o w r D A Q C o n n e c t o r... -
Page 25: Figure 3: Single-Ended Inputs
Chapter 2: Installation and Configuration Agnd Figure 3: Single-ended Inputs Note Unused channels should be shorted to ground using a 1- to 10-KΩ resistor. Differential Inputs: Differential inputs allow up to 32 channels. Each differential channel uses two analog channels — one analog channel connects to the positive input of the programmable gain amplifier, and the other to the negative. - Page 26 Chapter 2: Installation and Configuration Note When wiring applications to your PowerDAQ board, consider the following: • When working in an environment with electrical noise or when using gains, use differential input. • When working in an environment with electrical noise, use individually shielded twisted-pair wiring.
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Page 27: Test Program
Chapter 2: Installation and Configuration Note When using more than 4 PCI slots (standard PC), you will need a PCI bridge chip to support additional PCI slots. These bridge chips reduce the PCI bus throughput and will reduce your maximum sampling speed. -
Page 28: Connectors
Chapter 2: Installation and Configuration 2. Use the Analog In, Analog Out, Digital In, Digital Out, and Counters tabs to observe your application running on the board. Connectors PowerDAQ multifunction boards have four connectors: • 96-contact pin-less main connector (J1) Manufactured by: Fujitsu : PN# FCN-245P096-G/U (Male) http://www.fta.fujitsu.com/... -
Page 29: Table 5: J1 Connector (Single-Ended Mode)
Chapter 2: Installation and Configuration J1 Connector (Single-Ended Mode) AGND AGND AGND AOUT0 AGND 3 51 AGND AGND 4 52 AOUT1 DGND 5 53 AGND AGND AGND 6 54 AIN55 7 55 AIN54 AIN53 8 56 AIN52 AIN51 AIN50 AIN49 10 58 AIN48 AGND... -
Page 30: Table 6: J1 Connector (Differential Input Mode)
Chapter 2: Installation and Configuration J1 Connector (Differential Input Mode) AGND AGND AGND AOUT0 AGND 3 51 AGND AGND 4 52 AOUT1 DGND 5 53 AGND AGND AGND 6 54 AIN55 7 55 AIN54 AIN53 AIN52 8 56 AIN51 AIN50 AIN49 AIN48 10 58... -
Page 31: Table 7: Connector Pin Assignments For J2
Chapter 2: Installation and Configuration Connector Pin Assignments for J2 The J2 digital internal connector contains eight digital input and eight digital output lines. CTR0-IN CTR2-IN CTR0-OUT CTR2-OUT CTR0-GATE CTR2-GATE CTR1-GATE CTR1-IN CTR1-OUT 9 10 +5V (100 mA max) DGND DIN0 11 12 DIN1... -
Page 32: Table 8: Connector Pin Assignments For J4
Chapter 2: Installation and Configuration Connector Pin Assignments for J4 The J4 Connector contains eight digital input and eight digital output lines. DGND DGND DGND DGND DGND DGND DGND DGND DGND 9 10 +5V (100 mA max) 11 12 DGND DIN8 13 14 DIN9... -
Page 33: Table 9: Connector Pin Assignment For J6
Chapter 2: Installation and Configuration Connector Pin Assignments for J6 The J6 Interboard Synchronization Connector contains two pairs of clock signal lines: • The ADC Clock (also known as the conversion clock. • The Channel List Clock (also known as the scan clock or burst clock). -
Page 35: Architecture
Architecture... -
Page 36: Functional Overview
Chapter 3: Architecture Functional Overview PowerDAQ PD2-MF/MFS series have very extensive input modes, clocking and triggering capabilities as well as simultaneous subsystems operations. V o lt ag e A ln C alib ra t io n A ln Po w er... - Page 37 Chapter 3: Architecture Analog Input subsystem includes: • The Input multiplexor (MUX) selects which channels to acquire. The channel list (CL) FIFO controls the input muxes. PD2-MFS boards have sample-and-hold amplifiers (SHA) preceding the muxes. SHA amplifiers sample all input channels simultaneously and then hold the acquired voltages while the ADC converts channel by channel.
- Page 38 Chapter 3: Architecture • Timing, triggering and clocking controls allow you to select analog output rate and clock source. • Interrupt mechanism notifies the DSP about interrupt conditions. Digital Input/Output subsystem includes • 16-bit input register to read logical levels on digital input lines •...
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Page 39: Analog Input Subsystem
Chapter 3: Architecture Analog Input Subsystem The analog input front-end multiplexes multiplex the first stage of the input channels (64/16 single-ended or 32/8 differential) into a single, 12, 14 or 16-bit successive approximation ADC. The A/D subsystem also includes input modes, polarity, gain settings, channel gains, channel queue, trigger and clocking control. -
Page 40: Figure 8: Powerdaq Multifunction Board Front-End
Chapter 3: Architecture channel and gain control MUX A … Analog … to range input 0 control, calibration circuitry and … MUX B … SE/DF switch control Analog signal input N Figure 8: PowerDAQ Multifunction Board front-end MFS boards have sample and hold amplifiers (SHA) located at the signal inputs. -
Page 41: Figure 9: Powerdaq Sample And Hold Board Front-End
Chapter 3: Architecture Analog input 0 … to range control, calibration circuitry and ADC … … Analog input N SE/DF Gain channel switch contro select signal control signal signal signal Figure 9: PowerDAQ Sample and Hold Board front-end The major difference between MF and MFS boards are the SHAs. Sample and Hold ‘signal switches’... -
Page 42: Figure 10: Pd2-Mf Series Acquisition Process
Chapter 3: Architecture Channels Ch 0 Ch 1 Ch 2 Time Moment of digitizing Signal level at the moment of Figure 10: PD2-MF Series Acquisition Process Channels Ch 0 Ch 1 Ch 2 Sampl Time Hold Moment of digitizing Signal level... -
Page 43: Figure 11: Pd2-Mfs Acquisition Process
Chapter 3: Architecture Figure 11: PD2-MFS Acquisition Process Figures 10 and 11 show the differences in data acquired using MF and MFS boards. When a sine wave is applied to the channels 0, 1 and 2. and t is the time when the channel reading has happened. Minimum delay between them is limited by the rated speed of the board and can be calculated as 1/rate in kS (seconds). - Page 44 Chapter 3: Architecture Note Always use PowerDAQ MFS series of board if you require true difference between input channels levels and working with signals close to nyquist frequency. Note Complete timing tables for all PowerDAQ boards are located Appendix A.
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Page 45: Input Modes
Chapter 3: Architecture Input Modes Single Ended The PowerDAQ boards operate with either a single-ended or a differential input configuration. Single-ended inputs allow up to 64 channels and share a common low side, which is the analog ground. See Table Single ended inputs are shown diagrammatically in figure 12. -
Page 46: Figure 13: Differential Inputs
Chapter 3: Architecture Ain(+) Ain (RETURN) Agnd Figure 13: Differential Inputs Example: For a 16 channel PowerDAQ board in differential mode, channels 0 and 8 form the high and low inputs of input channel 0, channels 1 and 9 that of input channel 1. Differential inputs are shown See Table 6 for complete wiring instructions. -
Page 47: Input Ranges
Chapter 3: Architecture Input Ranges The PowerDAQ boards have four possible input ranges. These are global settings. UNIPOLAR BIPOLAR 0V to +10V - 10V to + 10V 0V to +5V -5V to +5V Table 10: Input Range Table Gain Settings You can set a gain for each channel prior to acquisition. -
Page 48: Channel List
Chapter 3: Architecture Channel List The Channel List contains sequences of channels to be acquired and their per channel gains. This sequence is known as the SCAN. The ADC Channel List can contain 1 to 256 channel entries. Configuration data for each channel will include the channel selection, gain, and slow bit setting. -
Page 49: Clocking
Chapter 3: Architecture Clocking The PowerDAQ board has two selectable base frequencies (11 MHz and 33 MHz) to clock acquisition. Lower frequencies are obtained by dividing the base frequency by a 24-bit number (from 1 to 16M). To calculate the result frequency use following formula: Timebase = Base Frequency / (divisor + 1) Acquisition is clocked by two signals: conversion start (CV Start) and channel list start (CL Start). -
Page 50: Table 14: Different Clocking Combinations
Chapter 3: Architecture Clock combination Typical use CL Clock CV Clock source source Continuous Acquire one set of data points (one scan). SW clock causes channel list to be executed once. The board will wait until next CL clock comes before restarting. Internal Continuous Continuous acquisition with accurate... -
Page 51: Triggering
Chapter 3: Architecture Triggering The Analog input subsystem needs a trigger signal to start and stop acquisition. The Trigger signal is selectable. It can be either software command or an external pulse. External trigger is edge-sensitive. You can select rising or falling edge to be active. If the board is set up to start on an external trigger, all clocks will be ignored until the pulse comes. -
Page 52: Adc Fifo
Chapter 3: Architecture Start Stop External TTL signal trigger trigger edge edge Rising Rising Rising Falling Falling Falling Falling Rising Acquisition started Acquisition stopped Table 15: External Trigger Modes ADC FIFO The PowerDAQ boards have an on-board FIFO. The FIFO could contain from 1kS (default) up to 32kS depending on the FIFO option purchased. -
Page 53: Data Format
Chapter 3: Architecture Data format Data in the data stream has the following format. Each two consecutive bytes contain a single sample from the A/D converter. Data is stored repeatedly sample by sample for all channels in the channel list. (Table 19 shows a PowerDAQ 16-bit board data format. For PowerDAQ 12-bit boards, only 12 LSBs (Least Significant Bits) are valid. -
Page 54: Table 20: Bit Weight Vs. Input Range
Chapter 3: Architecture The following calculations should be performed to convert the raw, stored hexadecimal data to scaled (Voltage) data: Determine the value of a single bit (“bit weight”) in Volts depending on the input range. 12-bit PowerDAQ 16-bit PowerDAQ (span)/4096 (span)/65535 0 - 5V unipolar (5V... - Page 55 Chapter 3: Architecture 4. Perform an arithmetical XOR with 0h0800 for PowerDAQ 12-bit boards and with 0h8000 for all PowerDAQ II and PowerDAQ 16-bit boards 5. Multiply by the “bit weight” from step 1 6. Add the “zero offset” from step 2 If a gain other than 1 was used for a selected channel, divide the value received by the gain factor (Doing this step last guarantees the maximal data accuracy.)
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Page 56: Analog Output Subsystem
Analog output subsystem contains two DACs (Digital to Analog Converters) and supports the following operating modes: Single Update The PowerDAQ PD2-MF(S) boards operate with either a single-update or streaming (waveform) output configuration. Single-update mode allows direct write access to the pair of 12-bit DACs. The update frequency is at least 1kHz for the single update mode. -
Page 57: Auto-Regeneration Waveform (Circular Waveform)
Channel List There is a fixed Channel List for the analog output on the PD2-MF(S) boards. The channel list always contains channel 0 and 1 and are updated simultaneously. -
Page 58: Clocking
Chapter 3: Architecture Value_To_Write = (HexValue1 << 12) OR (HexValue0) Clocking The analog output subsystem can be clocked using software command, internal 11 MHz base frequency or external trigger input line. In the case where the internal 11MHz timebase is used, calculate the output rate as follows: Timebase = 11 MHz / (divisor + 1) Every time a clock pulse comes, the board reads the next value from... -
Page 59: Digital Input/Output Subsystem
Chapter 3: Architecture Digital Input/Output Subsystem Digital Output subsystem contains one 16-bit output register. Digital outputs do not support clocked output, it can only be used in software- polled mode. The digital Input subsystem contains one 16-bit input register. Digital inputs do not support clocked input, it can only be used in software- polled mode. -
Page 60: Table 23: Digital Input Configuration Word
Chapter 3: Architecture Latch configuration is a 16-bit word, two bits for each one of eight sense inputs. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F: 1 in this position, the inputs are sensitive to falling edge R: 1 in this position, the inputs are sensitive to rising edge Table 23: Digital Input Configuration Word The Edge Detector and Latch Logic detect configured edges on the... -
Page 61: User Counter-Timer Subsystem
Chapter 3: Architecture User Counter-Timer Subsystem User counter-timer is based on the Intel 82C54 16-bit counter-timer chip. It contains three fully independent counter-timers. It’s fully dedicated for user applications and it is not used by any of the PowerDAQ systems. The logic allows you to select the clock and gate source for each of the three independent counter-timers. - Page 62 Chapter 3: Architecture The UCT is extremely useful in combination with the external clock and trigger lines. Using the UCT you can create very sophisticated acquisition setups.
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Page 63: Powerdaq Software Development Kit (Pd-Sdk)
PowerDAQ Software Development Kit (PD-SDK) -
Page 64: Powerdaq Software
Chapter 4: PowerDAQ Software (SDK) PowerDAQ Software PowerDAQ SDK Structure The installation will create the following directory structure in Program Files. This assumes you selected the SDK installation (default). PowerDAQ PowerDAQ root directory Applications Applications – ready to run Documentation Documents and manuals Software developers Kit (SDK) Examples... -
Page 65: Powerdaq Libraries
Chapter 4: PowerDAQ Software (SDK) Files: pwrdaq.sys device driver PowerDAQ DLLs The PowerDAQ software includes various DLLs (dynamic linked libraries) for Windows operating systems. The location of these DLLs is as follows: Windows 9x operating System Location: \windows\system directory Files: PwrDAQ32.dll 32-bit DLL PwrDAQ16.dll 16-bit DLL... -
Page 66: Powerdaq Include Files
Chapter 4: PowerDAQ Software (SDK) pd16bc45.lib - 16-bit Borland C++ 4.5x pwrdaq16.lib - 16-bit MSVC 1.5x PowerDAQ Include Files /include pdfw_def.h - firmware constant definition file for C/C++ pdfw_def.pas - firmware constant definition file for Borland Delphi pdfw_def.bas - firmware constant definition file for Visual Basic pwrdaq.h - driver constants and definitions file for C/C++ pwrdaq.pas... - Page 67 Chapter 4: PowerDAQ Software (SDK) /include/16-bit pwrdaq16.h - API function prototypes and structures file for 16-bit C/C++ pwrdaq.h - driver constants and definitions file for 16-bit C/C++ pdd_vb3.h - auxiliary functions to access PowerDAQ structures from within VB v.3.0 pd_hcaps.h - boards capabilities definition file for 16-bit C/C++...
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Page 68: Figure 16: Communication Between User Application And
Chapter 4: PowerDAQ Software (SDK) Communication between user application and PowerDAQ board PowerDAQ board samples Data Buffer PCI Bus Interface events PowerDAQ driver User Application PowerDAQ DLL Figure 16: Communication between user application and PowerDAQ board DSP – Digital Signal Processor controls all on board devices. User application communicates with the board via the PowerDAQ API encompassed into the PowerDAQ dynamic-link library (DLL). - Page 69 Chapter 4: PowerDAQ Software (SDK) Programming subsystems All PowerDAQ subsystems have two modes of operation: • Polled • Event-based Polled mode is preferred when the application does not need to be notified about hardware events. Event-based mode allows you to write truly asynchronous applications.
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Page 70: Analog Input Subsystem
Chapter 4: PowerDAQ Software (SDK) Analog Input Subsystem There are many ways of working with the analog input subsystem. Before you start programming your application, consider how you would like to use the board. To select the input mode you need to OR your analog input configuration word with the input mode selection constants. - Page 71 Chapter 4: PowerDAQ Software (SDK) Method A. Single scan operation See SDK Examples SimpleAin.c, simplescan.pas, simplescan.bas, vm64.pas, voltmeter.vbp, Vl16.cpp, PDGABoards.cpp This method is useful when you need to get one set of data points (one scan). This method allows you to acquire up to 100 scans per second, depending on the channel list size and maximal board speed.
- Page 72 Chapter 4: PowerDAQ Software (SDK) Acquisition - call the acquisition sequence using the timer or in a program loop. Allow all points in the scan to be acquired, then calculate how much time it takes to digitize the entire channel list. One channel takes (1 / maximum_board_rate) (s) to be digitized.
- Page 73 Chapter 4: PowerDAQ Software (SDK) Note The PowerDAQ boards have a special “slow bit” in the channel list. You might want to increase settling time for a particular channel with the high gain selected or a channel connected to a high output impedance signal.
- Page 74 Chapter 4: PowerDAQ Software (SDK) Method B. Burst Buffered Acquisition – One Shot See SDK Examples Stream2.c, SimpleExample.vbp This method is useful when you need to get one-shot data acquisition with significant delay between acquisition runs. For example if you need an application like an oscilloscope or FFT , run acquisition one time, then stop it, analyze data and run it again Method B is for you.
- Page 75 Chapter 4: PowerDAQ Software (SDK) dwCfg = (AIB_CVSTART0 | AIB_CVSTART1 | AIB_CLSTART1) for external clock Add AIB_INTCLSBASE constant to select 33 MHz base frequency instead of 11 MHz. Analog input event bits are defined in the file pwrdaq.h. Recommended event notification method: dwEvents = eFrameDone + eBufferDone + eBufferError + eStopped Your application will be notified when at least one frame is...
- Page 76 Chapter 4: PowerDAQ Software (SDK) your buffer with samples. When it returns event from the board you have to check what caused it • Check events _PdGetUserEvents(…) This function returns events for the subsystem specified (AnalogIn). Your code should analyze them and make a decision based on the result.
- Page 77 Chapter 4: PowerDAQ Software (SDK) _PdUnregisterBuffer(…) _PdFreeBuffer(…) Note External trigger. If you want your acquisition process to be started (or stopped) by an external pulse, connect your trigger source to the external trigger line setup your analog input configuration word (dwAInCfg) with trigger settings as stated below.
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Page 78: Table 24: Setting Up External Trigger
Chapter 4: PowerDAQ Software (SDK) Trigger type Configuration Start trigger rising AOB_STARTTRIG0 edge Start trigger falling AOB_STARTTRIG0 + AOB_STARTTRIG1 edge Stop trigger rising AOB_STOPTRIG0 edge Stop trigger falling AOB_ STOPTRIG0+ AOB_ STOPTRIG1 edge Table 24: Setting up External Trigger When the board is clocked from the low frequency internal timebase or external clock you might not get an immediate response because the board transfers data into the host memory only when the A/D FIFO becomes... - Page 79 Chapter 4: PowerDAQ Software (SDK) Method C. Continuous Acquisition using ACB See SDK Examples Stream2.c Method C uses the PowerDAQ Advanced Circular Buffer mechanism. Acquisition runs continuously and each time an event occurs, the application takes control. You can create separate threads in your application to run the acquisition process.
- Page 80 Chapter 4: PowerDAQ Software (SDK) WaitForSingleObject(hEventObject, Timeout) This function puts your program into a sleep mode and gives processor time to other processes. It is activated when the board signals an event or the timeout period has expired. The timeout period should be long enough to fill your buffer with samples.
- Page 81 Chapter 4: PowerDAQ Software (SDK) data in a one piece. This eliminates need of the user application to take care about data wrap around situations. _PdAInGetScans(…) has a side effect. When it’s called it marks frames it returns as “read”. This means that these frames can be reused for new data.
- Page 82 Chapter 4: PowerDAQ Software (SDK) How to find optimal frame size for data acquisition? The following should be taken into account when selecting the frame size. Events consume host CPU and on-board DSP time and a small frame decreases overall system performance, on the other hand, larger frames decrease event rates and you might need faster response especially in control-loop applications.
- Page 83 Chapter 4: PowerDAQ Software (SDK) Method D. Retrieving ‘always-fresh’ data using ACB recycled mode See SDK Examples Stream2.c Another very useful feature introduced by the PowerDAQ API’s ACB is recycled buffering mode. It allows frames to be overwritten with new data without reading it.
- Page 84 Chapter 4: PowerDAQ Software (SDK) Method F. Multi-board operations. Stream to disk applications See SDK Examples stream4.c, SingleBoardStreamBasic.vbp A special cable to synchronize data acquisition from several boards is required ( PD-CBL-SYNC4 See Appendix) . This cable has one master connector and three slaves.
- Page 85 Chapter 4: PowerDAQ Software (SDK) Method G. Combining Analog and Digital subsystems See SDK Examples SimpleTest.dpr The tricky part of combining digital and analog operations is the event handling. The PowerDAQ API has two sets of function to solve this. The first way is to set up all subsystem operations in a one thread and create an event using _PdSetPrivateEvent(…).
- Page 86 Chapter 4: PowerDAQ Software (SDK) Method Synchronous stimulus/response operation This is subset of Method A. Some applications require a analog stimulus to be applied to a system and a response read. You can do this by setting the analog input to start the scan from an external clock (CL Clock line) and the analog output to output the next data point on the external trigger line pulse.
- Page 87 Chapter 4: PowerDAQ Software (SDK) When starting out, first recognize that a driver for a data acquisition card differs from one for a printer, CD-ROM or other peripheral in one fundamental way: real-time operation. A printer can wait before it gets the next data to print; a CD-ROM can pause for a short while to let some other activity go on.
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Page 88: Analog Output Subsystem
Chapter 4: PowerDAQ Software (SDK) Analog Output Subsystem There are four update modes for the analog output subsystem: • Polled I/O update mode • Buffered event-based waveform mode using PCI interrupts • Buffered polled-I/O waveform mode • Auto-retriggerable waveform mode Method A. - Page 89 Chapter 4: PowerDAQ Software (SDK) Method B. Buffered event-based waveform mode using PCI interrupts See SDK Examples AOEvents.c, AEOutBlk.vbp Buffered event-based waveform mode allows you to generate any continuous waveforms. When the on-board output FIFO is less than half full, the board sends an interrupt to the host to request additional data.
- Page 90 Chapter 4: PowerDAQ Software (SDK) • Enable and start analog output waveform generation _PdAOutEnableConv(…) use 1 as dwEnable _PdAOutSwStartTrig(…) Note Use _PdAOutSwStartTrig() start waveform generation by software. If you wish to synchronize analog output signal with external trigger, set appropriate flags _PdAOutSetCfg() (flags...
- Page 91 Chapter 4: PowerDAQ Software (SDK) Stop acquisition • Issue a stop trigger if external trigger was not configured _PdAOutSwStopTrig() • Disable D/A conversions _PdAOutEnableConv(…) use 0 (false) as dwEnable De-Initialize • Disable interrupt (if no other subsystem uses interrupt at that time) _PdAdapterEnableInterrupt(…) use dwEnable = 0 •...
- Page 92 Chapter 4: PowerDAQ Software (SDK) Method C. Buffered polled-I/O waveform mode See SDK Example AoutBlock.vbp Buffered polled-I/O waveform mode does not require an event handler. Instead, the analog output subsystem is initialized and the initial data is written to the output buffer (2048 samples maximum). After the subsystem and buffer have been initialized, the application continues to write samples to the buffer.
- Page 93 Chapter 4: PowerDAQ Software (SDK) • Continue waveform generation _PdAOutEnableConv(…) use 1 as dwEnable _PdAOutSwStartTrig(…) • Sleep for a while using Sleep(…) Win32 API call to give up processor time to other processes Sleep(n) – time for process to sleep depends on output rate.
- Page 94 Chapter 4: PowerDAQ Software (SDK) Method D. Auto-retriggerable waveform mode (no CPU usage) See SDK Example SimpleTest.dpr Auto-regeneration waveform mode is used to create fixed-length waveforms (2048 samples/scans maximum) without using any CPU cycles in the host PC. After an application writes datum to the buffer, the board starts to output the waveform, which will be restarted automatically when the buffer pointer reaches the end of the buffer.
- Page 95 Chapter 4: PowerDAQ Software (SDK) _PdAOutEnableConv(…) use 1 as dwEnable _PdAOutSwStartTrig(…) Stop acquisition • Reset analog output subsystem _PDAOutReset(…) Note Board will stop waveform generation when it reaches the end of the buffer. To convert float voltages to raw values use function PdAOutVoltsToRaw(…)
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Page 96: Digital Input/Output Subsystems
Chapter 4: PowerDAQ Software (SDK) Digital Input/Output Subsystems The digital input/output subsystem can be used in two ways. Method A: 16-bit digital input and digital output polled configuration. Note: The digital subsystem has no clocked operations available. Method B: Set up an input configuration and the digital input fires an event when it detects a specified edge on the selected input line. - Page 97 Chapter 4: PowerDAQ Software (SDK) Configuration word is explained in Digital I/O Architecture section of this manual. • Read status of digital input latch _PdDInGetStatus(…)function returns current state of the digital input lines in a single byte and digital input latch register in the other byte. If the specified edge was detected, the latch contains “1”...
- Page 98 Chapter 4: PowerDAQ Software (SDK) Method B. Generate event when specified edge is detected See SDK Example DIEvents.c This method is very similar in setup parameters with Method A. The difference is that you should additionally enable and set up event notification.
- Page 99 Chapter 4: PowerDAQ Software (SDK) _PdGetUserEvent(…) should return eDInEvent flag in the status word. • Read status of digital input latch _PdDInGetStatus(…) function returns current state of the digital input lines in a one byte and digital input latch register in the other byte. If specified edge was detected, the latch contains “1”...
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Page 100: User Counter-Timer Subsystem
Chapter 4: PowerDAQ Software (SDK) User Counter-Timer Subsystem The User Counter-Timer subsystem can be used in many different ways. Counter-timers are fully dedicated to the user tasks. Three on-board counter-timers can be set up to any configurable Intel 82C54 chip mode. - Page 101 Chapter 4: PowerDAQ Software (SDK) _PdUctReset(…)clears latch configuration register Set up UCT configuration • Set up edge-sensivity configuration _PdUctSetCfg(…)use this function to set up UCT uct_progr.c configuration. Refer definition _PdAdapterEnableInterrupt(…) with dwEnable = 1 _PdUctSetPrivateEvent(…)set up event object _PdSetUserEvent(…) CounterTimer subsystem name.
- Page 102 Chapter 4: PowerDAQ Software (SDK) Note To write to the counter-timer, an input clock must be applied to appropriate UCT. You can control the gate using the API call _PdUctSwSetGate(…).
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Page 103: Powerdaq Example Programs
Chapter 4: PowerDAQ Software (SDK) PowerDAQ Example Programs A complete range of sample programs with source code is included with your PowerDAQ board. For complete details on programming the PowerDAQ board, refer to the PowerDAQ Software Manual Note Listed below are summary of a few examples. Please review the installation directories for new examples or online at www.PowerDAQ.com Visual C++ examples... - Page 104 Chapter 4: PowerDAQ Software (SDK) SimpleTest application which allows Analog Input, Analog Output, Digital Input, Digital Output and Counter Timer operation. This program also allows simultaneous subsystem operation. Borland C++ Builder examples Versions supported: Inprise/Borland 3.5 Examples supplied: Stream4.exe – continuous acquisition and stream to disk application. Note The include files for the above languages may have the same file name.
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Page 105: Third Party Software Support
Chapter 4: PowerDAQ Software (SDK) Third Party Software Support The PowerDAQ CD contains drivers for most of the popular third party software packages. The installation procedure automatically detects if you have installed any of the third party packages and will install the drivers and examples automatically If you install a third party software package after installing the PowerDAQ software, you must re-install the PowerDAQ software to... -
Page 107: Calibration
Calibration... -
Page 108: Calibration
Chapter 5: Calibration Calibration Overview This chapter contains information on the calibration procedures for the A/D and D/A subsystems on the PowerDAQ series of boards. When to calibrate These procedures should be performed at six-month intervals. It is highly recommended to send board back to UEI, Inc. calibration facility for recalibration. -
Page 109: Appendix A: Specifications
Appendix A: Specifications... - Page 110 Appendix A: Specifications...
- Page 111 Appendix A: Specifications PowerDAQ II Board Acquisition Timing The table below shows continuous acquisition and timing delays controlled by the PowerDAQ II onboard logic. These timings guarantee accuracy. PD2-MF Series Timing: UEI Model Res / Speed / Gain Fast Acq Slow Acq...
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Page 113: Appendix B: Accessories
Appendix B: Accessories... -
Page 114: Accessories
Appendix B: Accessories Accessories The following accessories are available for the PowerDAQ boards. Screw Terminal Panels Screw Terminal Panel with 96-pin and 37-pin PD-STP-96 connector for 64-channel boards Complete Kit: Includes PD-STP-96, PD-CBL-96 PD-STP-96-KIT and PD-CBL-37 for 64-channel boards Screw Terminal Panel with 96-pin and 37-pin PD-STP-9616 connector for 4/8/16-channel boards Complete Kit: Includes PD-STP-9616, PD-CBL-96... -
Page 115: Thermocouple Input Racks
Appendix B: Accessories Thermocouple Input Racks 16-channel Isolated Thermocouple Input Rack— PD-TCR-16-J Type J 16-channel Isolated Thermocouple Input Rack— PD-TCR-16-K Type K 5B/7B/OEM Distribution Panels Connects 16- or 64-channel PowerDAQ II board PD-5BCONN to 1 to 4, 5B-xx racks Connects 16- or 64-channel PowerDAQ II board PD-7BCONN to 1 to 4, 7B-xx racks Connects 16- or 64-channel PowerDAQ II board... -
Page 116: Cables
Appendix B: Accessories Cables 96-way pinless, 1m round, shielded cable with PD-CBL-96 metal cover plates 96-way pinless, 6 ft round, shielded cable with PD-CBL-96-6FT metal cover plates 96-way pinless, 9 ft round, shielded cable with PD-CBL-96-9FT metal cover plates DIO cable set: 37-way, 1m D-sub cable, Internal PD-CBL-37 cable with mounting bracket DIO cable: 37-way, 1m internal cable with... -
Page 117: Signal Conditioning Expansion Units
Appendix B: Accessories Signal Conditioning Expansion Units PD-SCXU-F8 8 Anti-aliasing filters PD-SCXU-F16 16 Anti-aliasing filters PD-SCXU-G8 8 Programmable gain amplifiers PD-SCXU-G16 16 Programmable gain amplifiers 8 Anti-aliasing filters combined with 8 PD-SCXU-FP8 programmable gain amplifiers 8 Anti-aliasing filters and 8 programmable gain PD-SCXU-F8-P8 amplifies (not combined) 16 Anti-aliasing filters combined with 16... -
Page 119: Appendix C: Application Notes
Appendix C: Application Notes... -
Page 120: Application Note: 1
Appendix C: Application Notes Application Note: 1 PowerDAQ Advanced Circular Buffer (ACB) The Advanced Circular Buffer solves many of the problems associated with high throughput data acquisition on a multi-threaded /multi- tasking OS. For simplicity, data acquisition as an input process is discussed, however, the same concepts can be applied to output signal generation. -
Page 121: Single Buffer
Appendix C: Application Notes To receive notification on a sample or scan count boundary, the buffer is segmented into frames. Whenever the data transferred to the buffer crosses a frame boundary, the driver sends an event to the application. This event "wakes up" the application thread that is responsible for processing data in the buffer. - Page 122 Appendix C: Application Notes Circular Buffer In the Circular Buffer mode the buffer head and tail wrap to the beginning of the buffer when the end is reached. Data is written at the location pointed to by head and the head pointer is incremented and likewise data is read from the location pointed to by the tail and the tail pointer is incremented.
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Page 123: Figure 17: Advanced Circular Buffer
Appendix C: Application Notes Driver Asserts Frame Done Events Advanced Circular When Data Written Passes Frame Buffer Boundry Board/Driver Write New Data At Buffer Head Application Buffer Head Reads Data From Buffer Tail Buffer Tail Frame Markers Figure 17: Advanced Circular Buffer While the Advanced Circular Buffer may appear as a much different buffering mechanism as compared to the much simpler single and double buffer mechanisms, in essence, it is actually a superset of the... -
Page 124: Application Note: 2
Appendix C: Application Notes Application Note: 2 PD-BNC-xx wiring options: Voltage dividers In order to build a voltage divider, resistors should be installed into the R0A, R8A and R0C positions, for the channel 0 and channel 8 pair, and similarly for the other pairs. Note that as supplied by the factory, the RxA resistors have zero Ohm jumpers installed. -
Page 125: Appendix D: Warranty
Appendix D: Warranty... -
Page 126: Overview
EN55011 • EN50082-1 Life Support Policy UNITED ELECTRONIC INDUSTRIES' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE LEGAL AFFAIRS DEPARTMENT OF UNITED ELECTRONIC INDUSTRIES CORPORATION. As used herein: 1. - Page 127 WITH RESPECT TO THE PRODUCTS AND IS IN LIEU OF ALL OTHER WARRANTIES. LIABILITIES AND REMEDIES, EXCEPT AS THUS PROVIDED, UNITED ELECTRONIC INDUSTRIES DISCLAIMS ALL WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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Page 129: Appendix E: Glossary
Appendix E: Glossary... -
Page 130: Glossary
Appendix E: Glossary Glossary Analog-to-digital. Analog-to-Digital Converter. integrated circuit that converts analog voltage to a digital number. ADC Conversion The process of converting a single analog input to a digital value. ADC Conversion Start Signal used to start the conversion process of an analog input to a digital value. - Page 131 Appendix E: Glossary (2) Software - A property of a function that begins an operation and returns prior to the completion or termination of the operation. Background Acquisition Data is acquired by a DAQ system while another program or processing routine is running without apparent interruption.
- Page 132 Appendix E: Glossary amount of memory required to store one byte of data. Cache High-speed processor memory that buffers commonly used instructions or data to increase processing throughput. Channel List A variable length list of 1 to 256 channels and their associated gains and “slow bits”...
- Page 133 Appendix E: Glossary Component Software An application that contains one or more component objects that freely interact with other component software. Examples include OLE- enabled applications such as Microsoft Visual Basic and OLE Controls for virtual instrumentation in Component Works. Conversion Time The time required, in an analog input or output system, from the moment a...
- Page 134 Appendix E: Glossary DAC Conversion Start signal used to start the conversion process of digital value to an analog output. The source of this signal can be either an internal DAC synchronous clock external asynchronous signal. This is a common signal fed to both DACs.
- Page 135 Appendix E: Glossary Differential Non-linearity: A measure in LSB of the worst-case deviation of code widths from their ideal value of 1 LSB. Direct Memory Access: A method by which data can be transferred to/from computer memory from/to a device or memory on the bus while the processor does something else.
- Page 136 Appendix E: Glossary opaque areas, a light source, and a photo detector. EPROM Erasable Programmable Read-Only Memory: ROM that can be erased (usually by ultraviolet light exposure) and reprogrammed. Events Signals or interrupts generated by a device to notify another device of an asynchronous event.
- Page 137 Appendix E: Glossary program by means of graphical screen displays. GUIs can resemble the front panels of instruments or other objects associated with a computer program. Handler A device driver that is installed as part operating system computer. Hardware The physical components of a computer system, such as the circuit boards, plug-in boards,...
- Page 138 Appendix E: Glossary Integral Control A control action that eliminates the offset inherent in proportional control. Integrating ADC An ADC whose output code represents the average value of the input voltage over a given time interval. Interpreter A software utility that executes source code from a high-level language such as Basic, C or Pascal, by reading one line at a time and executing the...
- Page 139 Appendix E: Glossary Kilo, the prefix for 1,024, or 210, used with B in quantifying data or computer memory. kbytes/s A unit for data transfer that means 1,000 or 103 bytes/s. Linearity The adherence of device response to equation where =response, S = stimulus, and K = a constant.
- Page 140 Appendix E: Glossary Noise An undesirable electrical signal. Noise comes from external sources such as the AC power line, motors, generators, transformers, fluorescent lights, soldering irons, dis-plays, computers, electrical storms, welders, radio transmitters, and internal sources such as semiconductors, resistors, and capacitors.
- Page 141 Appendix E: Glossary Output Settling Time The amount of time required for the analog output voltage to reach its final value within specified limits. Output Slew Rate The maximum rate of change of analog output voltage from one level to another.
- Page 142 Appendix E: Glossary networking protocols, special- purpose digital and analog I/O ports. Plug and Play ISA A specification prepared by Microsoft, Intel, and other PC-related companies that will result in PCs with plug-in boards that can be fully configured in software, without jumpers or switches on the boards.
- Page 143 Appendix E: Glossary through a communications channel, such as the GPIB. Quantization Error The inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process. Real Time A property of an event or system in which data is processed as it is acquired in-stead of being accumulated and processed at a later time.
- Page 144 Appendix E: Glossary Single-Ended: A term used to describe an analog input that is measured with respect to a common ground. Scan Set of the channels, or data point, to be acquired at the same time. Self-Calibrating DAQ board that calibrates its own A/D and D/A circuits with and external reference source.
- Page 145 Appendix E: Glossary Subroutine A set of software instructions executed by a single line of code that may have input and/or output parameters. Successive-Approximation ADC that sequentially compares a series of binary-weighted values with an analog input to produce an output digital word in n steps, where n is the bit resolution of the ADC.
- Page 146 Appendix E: Glossary Thermocouple A temperature sensor created by joining two dissimilar metals. The junction produces a small voltage as a function of the temperature. Throughput Rate The data, measured in bytes/s, for a given continuous operation. Transducer A device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow,...
- Page 147 Index Index _PdGetUserEvents ....64 _PdImmediateUpdate .... 70 _PdRegisterBuffer ....62 _PdAdapterEnableInterrupt ... 77 _PdSetPrivateEvent ....73 _PdAInAsyncInit.....65 _PdUctReset ......89 _PdAInAsyncStart ... 64, 65 _PdUctSerCfg ......89 _PdAInAsyncStop....65 _PdUctSetPrivateEvent...89 _PdAInClearPrivateEvent..65 _PdUctSetPrivateEvent... 73 _PdAInEnableConv....59 _PdUnregisterBuffer....65 _PdAInEnableTimer....70 _PdAInGet Samples ....60 _PdAInSetCfg ......59 _PdAInSetChList.....59 82C54........
- Page 148 Index Calibration ......95 FIFO Upgrades ......6 Calibration DACs ....26 Frame size ......69 CE Mark Fujitsu Connector ....17 CE Mark Certification ..117 Functional Overview....25 Channel list.......26, 37 Channel list D/A ....45 Circular waveform....45 Gain settings ......36 CL start clock ......38 Gate source......
- Page 149 PD CAL Application ....95 pd_hcaps.bas ......55 pd_hcaps.h ..... 54, 55 Sample and Hold Amplifiers .. 29 pd_hcaps.pas ......54 SDK structure ......52 PD2-MF Series ......3 Simple Test......16 PD2-MFS Series ......4 Single Ended..... 13, 34 PD2-MFS Series Gain Option ...5 Single scan operation..... 59 PD2-MFS-DGx ......29...
- Page 150 Index voltage divider....... 114 Waveform – auto retriggerable ....... 82 Waveform – buffered event based ........77 WaitForSingleObject ....64 Waveform – buffered polled WaitForSingleObject ....73 I/O........80 Warranty ....... 116 Windows 9x ......53...
- Page 151 PowerDAQ II Series PCI DAQ Board User Manual Reader Evaluation We are committed to improving the quality of our documentation, in order to serve you better. Your feedback will help us in the effort. Thanks for taking the time to fill out and return this form. Is the manual well organized? Can you find information easily? Were you able to install the PowerDAQ...
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