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Signal
Pin# Description
PCI_STOP#
D34
PCI_PAR
D32
PCI_PERR#
C34
PCI_REQ0#
C22
PCI_REQ1#
C19
PCI_REQ2#
C17
PCI_REQ3#
D20
PCI_GNT0#
C20
PCI_GNT1#
C18
PCI_GNT2#
C16
PCI_GNT3#
D19
PCI_RESET#
C23
PCI_LOCK#
C35
PCI_SERR#
D33
PCI_PME#
C15
PCI_CLKRUN#
D48
PCI_IRQA#
C49
PCI_IRQB#
C50
PCI_IRQC#
D46
PCI_IRQD#
D47
PCI_CLK
D50
PCI_M66EN
D49
COM Express® Carrier Board Design Guide
PCI bus STOP control line, active low
PCI bus parity
Parity Error: An external PCI device drivers
PERR# by driving it low, when it receives data that
has a parity error.
PCI bus master request input line, active low
PCI bus master request input line, active low
PCI bus master request input line, active low
PCI bus master request input line, active low
PCI bus master grant output line, active low
PCI bus master grant output line, active low
PCI bus master grant output line, active low
PCI bus master grant output line, active low
PCI Reset output, active low
PCI Lock control line, active low
System Error: SERR# may be pulsed active by any
PCI device that detects a system error condition
PCI Power Management Event:
PCI peripherals drive PME# to low to wake up the
system from low-power states S1-S5
Bidirectional pin used to support PCI clock run
protocol for mobile systems.
PCI interrupt request line A
PCI interrupt request line B
PCI interrupt request line C
PCI interrupt request line D
PCI 33MHz clock output
Module input signal that indicates whether a Carrier
Board PCI device is capable of 66MHz operation.
It is pulled to ground by Carrier Board device or by
slot card, if one of the devices is NOT capable of
66MHz operation.
I/O
Remarks
I/O 3.3V
I/O 3.3V
I/O 3.3V
I 3.3V
I 3.3V
I 3.3V
I 3.3V
O 3.3V
O 3.3V
O 3.3V
O 3.3V
Asserted during
O 3.3V_SBY
system reset
I/O 3.3V
I/O 3.3V
I 3V3_SBY
I/O 3.3V
I 3.3V
I 3.3V
I 3.3V
I 3.3V
O 3.3V
I 3.3V
69
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