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IBASE Technology COM EXPRESS ET976 Design Manual

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COM EXPRESS
CARRIER BOARD
DESIGN GUIDE
Version 1.0
(January 2022)

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Summary of Contents for IBASE Technology COM EXPRESS ET976

  • Page 1 COM EXPRESS CARRIER BOARD DESIGN GUIDE Version 1.0 (January 2022)
  • Page 2 Disclaimer IBASE reserves the right to make changes and improvements to this document without prior notice. Every effort has been made to ensure the information in the document is correct; however, IBASE does not guarantee this document is error-free. IBASE assumes no liability for incidental or consequential damages arising from misapplication or inability to use the information contained herein, nor for any infringements of rights of third parties, which may result from its use.

  • Page 3: Table Of Contents

    Table of Contents  Chapter 1  General Information ..............1  ABOUT COM EXPRESS ................1     Chapter 2 COM Express Interfaces ............... 2  General Purpose PCIe Lanes ..............3     2.1.1 Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors ..3  ...
  • Page 4 LVDS ......................29     2.8.1 Signal Definitions ................29     2.8.2 Reference Schematics ............... 30     2.8.3 Routing Considerations ..............32     Embedded DisplayPort (eDP) ..............33     2.9.1 Signal Definitions ..................33     2.9.2 Reference Schematics ................
  • Page 5   2.16 General Purpose Serial Interface ............. 53     2.16.1 Signal Definitions ................53     2.16.2 Reference Schematics ............... 54     2.16.2.1 General Purpose Serial Port Example ..........54   2.16.3 Routing Considerations ..............56     2.17 CAN Interface ..................
  • Page 6 COM Express Connector (Tyco) ......錯誤! 尚未定義書籤。     This page is intentionally left blank. COM Express® Carrier Board Design Guide...

  • Page 7: Chapter 1 General Information

    General Information Chapter 1 General Information This design guide provides suggestions on designing IBASE COM-Express products including carrier boards and systems. For other carrier board schematic guidelines please refer to the full specification in the PICMG® COM Express® Carrier Board Design Guide.

  • Page 8: Chapter 2 Com Express Interfaces

    Chapter 2 COM Express Interfaces The information provided in this chapter includes:  General Purpose PCIe Lanes  PEG (PCI Express Graphics)  Digital Display Interfaces   USB Ports  USB 3.0  SATA  LVDS  Embedded DisplayPort (eDP) ...

  • Page 9: General Purpose Pcie Lanes

    2.1 General Purpose PCIe Lanes 2.1.1 Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors Figure 1: PCIe Rx Coupling Capacitors The coupling caps for the Module PCIe TX lines are to be on the Module, as indicated in the COM Express specification.

  • Page 10: Schematic Examples

    2.1.2 Schematic Examples Figure 2: PCI Express x1 Slot Example COM Express® Carrier Board Design Guide...
  • Page 11 Figure 3: PCI Express x4 Slot Example COM Express® Carrier Board Design Guide...
  • Page 12 Figure 4: PCIe Mini Card Reference Circuitry COM Express® Carrier Board Design Guide...

  • Page 13: Pci Express Routing Considerations

    2.1.3 PCI Express Routing Considerations New Carrier designs route the PCIe lanes with 85Ω (+/- 15%) differential impedance. Past designs for Gen1 and Gen2 signaling used 92Ω (+/- 10%) differential impedance. Gen1 designs used 100Ω (+/- 20%) differential impedance. New designs use 85Ω (+/- 15%) differential impedance for Gen1, Gen2 and Gen3 signaling.

  • Page 14: Peg (Pci Express Graphics)

    2.2 PEG (PCI Express Graphics) Table 1: PEG Signal Definitions Signal Pin# Description Remarks PEG_RX0+ PEG channel 0, Receive I PCIE Type 2 SDVO_TVCLKIN+ PEG_RX0- Input differential pair. Shared with: SDVO_TVCLKIN- PEG_TX0+ PEG channel 0, Transmit O PCIE Type 2 SDVOB_RED+ PEG_TX0- Output differential pair.
  • Page 15 Signal Pin# Description Remarks PEG_RX12+ PEG channel 12, Receive I PCIE PEG_RX12- Input differential pair. PEG_TX12+ PEG channel 12, Transmit O PCIE PEG_TX12- Output differential pair. PEG_RX13+ PEG channel 13, Receive I PCIE PEG_RX13- Input differential pair. PEG_TX13+ PEG channel 13 Transmit O PCIE PEG_TX13- Output differential pair.

  • Page 16: Reference Schematics

    2.2.1 Reference Schematics Figure 5: x1, x4, x8, x16 Slot COM Express® Carrier Board Design Guide...

  • Page 17: Digital Display Interfaces

    2.3 Digital Display Interfaces Module Types 6 and 10 use Digital Display Interfaces (DDI) to provide DisplayPort, HDMI/DVI, and SDVO interfaces. Type 10 Modules can contain a single DDI (DDI[0]) that can support DisplayPort, HDMI/DVI, and SDVO. Type 6 Modules can contain up to 3 DDIs (DDI[1:3]) of which DDI[1:3] can support DisplayPort, HDMI/DVI and DDI[1] can support DisplayPort, HDMI/DVI, and SDVO.

  • Page 18: Reference Schematic

    2.3.1.1 Reference Schematic Figure 6: DisplayPort Reference Schematics COM Express® Carrier Board Design Guide...
  • Page 19 Figure 7: HDMI Example (1) COM Express® Carrier Board Design Guide...
  • Page 20 Figure 7: HDMI Example (2) COM Express® Carrier Board Design Guide...
  • Page 21 Figure 8: DVI Example (1) COM Express® Carrier Board Design Guide...
  • Page 22 Figure 8: DVI Example (2) COM Express® Carrier Board Design Guide...

  • Page 23: Routing Considerations

    Figure 8: DVI Example (3) 2.3.1.2 Routing Considerations For the DisplayPort interconnection between the COM Express Module and the DisplayPort connector or the level shifter, refer to the COM Express Carrier Design Guide, Rev. 2.0 / December 6, 2013, Section 6.5.6 'DisplayPort Trace Routing Guidelines' on page 186 for details.

  • Page 24: Sdvo

    2.3.2 SDVO 2.3.2.1 Signal Definitions Type 6 Modules allow one SDVO port on DDI[1]. The DDI port needs to be configured to be used as SDVO usually via the Module's BIOS. On Type 2 Modules the pins for SDVO ports B and C are shared with the PEG port. Table 3: SDVO Port Configuration SDVO Port B SDVO Port C...

  • Page 25: Lan

    2.4 LAN In general, COM Express Modules provide at least one LAN port. The 8-wire 10/100/1000BASE-T Gigabit Ethernet interface compliant to the IEEE 802.3-2005 specification is the preferred interface for this port, with the COM Express Module PHY responsible for implementing auto-negotiation of 10/100BASE-TX vs 10/100/1000BASE-T operation.

  • Page 26: Reference Schematics

    2.4.2 Reference Schematics Figure 10: Magnetics Integrated Into RJ-45 Receptacle 2.4.3 Routing Considerations The 8-wire PHY / MDI circuit is required to meet a specific waveform template and associated signal integrity requirements defined in the IEEE 802.3-2005 specification. Routing rules should be observed on the Carrier Board.

  • Page 27: Usb Ports

    2.5 USB Ports 2.5.1 Signal Definitions Table 5: USB Signal Description Signal Pin Description Remarks USB0+ A46 USB Port 0, data + or D+ I/O USB mandatory on Module USB0- A45 USB Port 0, data - or D- I/O USB mandatory on Module USB1+ B46 USB Port 1, data + or D+...

  • Page 28: Reference Schematics

    2.5.2 Reference Schematics Figure 11: USB Reference Design 2.5.3 Routing Considerations Route USB signals as differential pairs, with a 90-Ω differential impedance and a 45-Ω, single- ended impedance. A USB pair is routed on a single layer adjacent to a ground plane. USB pairs should not cross plane splits.

  • Page 29: Usb 3.0

    2.6 USB 3.0 2.6.1 Signal Definitions Table 5: USB 2.0 Differential Lines Signal Pins Pins Description USB0+ USB Port 0, data + or D+ I/O USB USB0- USB Port 0, data - or D- I/O USB USB1+ USB Port 1, data + or D+ I/O USB USB1- USB Port 1, data - or D-...

  • Page 30: Reference Schematics

    2.6.2 Reference Schematics Figure 12: USB 3.0 Example (1) COM Express® Carrier Board Design Guide...
  • Page 31 Figure 12: USB 3.0 Example (2) COM Express® Carrier Board Design Guide...

  • Page 32: Routing Considerations

    2.6.3 Routing Considerations Route USB data signals as differential pairs, with a 90-Ω differential impedance and a 45-Ω, single-ended impedance. Route USB SuperSpeed signals as differential pairs, with an 85-Ω differential impedance and a 50-Ω, single-ended impedance. A USB pair is routed on a single layer adjacent to a ground plane.

  • Page 33: Sata

    2.7 SATA 2.7.1 Signal Definitions Table 8: SATA Signal Description Signal Description Remarks SATA0_RX+ Serial ATA channel 0 I SATA SATA0_RX- Receive input differential pair. SATA0_TX+ Serial ATA channel 0 O SATA SATA0_TX- Transmit output differential pair. SATA1_RX+ Serial ATA channel 1 I SATA SATA1_RX- Receive input differential pair.

  • Page 34: Reference Schematic

    2.7.2 Reference Schematic Figure 13: SATA Connector Diagram 2.7.3 Routing Considerations Route SATA signals as differential pairs, with an 85 Ω differential impedance and a 50 Ω, single- ended impedance. Ideally, a SATA pair is routed on a single layer adjacent to a ground plane. SATA pairs should not cross plane splits.

  • Page 35: Lvds

    2.8 LVDS 2.8.1 Signal Definitions Table 9: LVDS Signal Descriptions Signal Description LVDS_A0+ LVDS channel A differential signal pair 0 O LVDS LVDS_A0- LVDS_A1+ LVDS channel A differential signal pair 1 O LVDS LVDS_A1- LVDS_A2+ LVDS channel A differential signal pair 2 O LVDS LVDS_A2- LVDS_A3+...

  • Page 36: Reference Schematics

    2.8.2 Reference Schematics Figure 14: LVDS Reference Schematic (1) COM Express® Carrier Board Design Guide...
  • Page 37 Figure 14: LVDS Reference Schematic (2) COM Express® Carrier Board Design Guide...

  • Page 38: Routing Considerations

    2.8.3 Routing Considerations Route LVDS signals as differential pairs (excluding the five single-ended support signals), with a 100-Ω differential impedance and a 55-Ω, single-ended impedance. An LVDS pair should be routed on a single layer adjacent to a ground plane. LVDS pairs should not cross plane splits. Keep layer transitions to a minimum.

  • Page 39: Embedded Displayport (Edp)

    2.9 Embedded DisplayPort (eDP) 2.9.1 Signal Definitions eDP is available in Type 6 and type 10 pin-outs as an alternative to the LVDS A channel. The Module can provide LVDS only, eDP only or Dual-Mode for both interfaces. Refer to the Module documentation for the supported interfaces.

  • Page 40: Reference Schematics

    2.9.2 Reference Schematics Figure 15: eDP Reference Schematic COM Express® Carrier Board Design Guide...

  • Page 41: Routing Considerations

    The reference schematic provides a generic eDP interface. The eDP connector used in the design is an example only. Other connectors can be used based on the design requirements. JP5 selects 3.3 or 5V for the panel power. R336 ensures that panel power is disabled when the Module is powering up and before the signal is actively driven.

  • Page 42: Vga

    2.10 2.10.1 Signal Definitions Table 10: VGA Signal Description Signal Pin HDSUB1 Description Remarks Red component of analog DAC monitor VGA_RED O Analog Analog output output, designed to drive a 37.5Ω equivalent load. Green component of analog DAC VGA_GRN O Analog Analog output monitor output, designed to drive a 37.5Ω...

  • Page 43: Vga Reference Schematics

    2.10.2 VGA Reference Schematics Figure 16: VGA Reference Schematics (1) COM Express® Carrier Board Design Guide...
  • Page 44 Figure 16: VGA Reference Schematics (2) COM Express® Carrier Board Design Guide...

  • Page 45: Routing Considerations

    2.10.3 Routing Considerations 2.10.3.1 RGB Analog Signals The RGB signal interface of the COM Express Module has three identical 8-bit digital-to- analog converter (DAC) channels. One each for the red, green, and blue components of the monitor signal. Each channel should have a 150Ω ±1% pull-down resistor connected from the DAC output to the Carrier Board ground.

  • Page 46: Digital Audio Interfaces

    2.11 Digital Audio Interfaces Table 11: Audio Codec Signal Descriptions Signal Description AC/HDA_RST# CODEC Reset. O 3.3V Suspend CMOS AC/HDA_SYNC Serial Sample Rate Synchronization. O 3.3V CMOS AC/HDA_BITCLK 24 MHz Serial Bit Clock for HDA CODEC. O 3.3V CMOS AC/HDA_SDOUT Audio Serial Data Output Stream.

  • Page 47: Reference Schematics

    2.11.1 Reference Schematics 2.11.1.1 High Definition Audio Figure 18: HDA Example Schematic (1) COM Express® Carrier Board Design Guide...
  • Page 48 Figure 18: HDA Example Schematic (2) COM Express® Carrier Board Design Guide...

  • Page 49: Routing Considerations

    2.11.2 Routing Considerations Route traces with a target impedance of 55Ω with a tolerance of ±15%. Pay attention to ground return paths for the analog signals. Digital signals routed in the vicinity of the analog audio signals should not cross the power plane split lines. The analog and digital signals are to be far from each other.

  • Page 50: Lpc Bus - Low Pin Count Interface

    2.12 LPC Bus – Low Pin Count Interface 2.12.1 Signal Definition Table 12: LPC Interface Signal Descriptions Signal Description Comment LPC_SERIRQ LPC serialized IRQ. I/O 3.3V CMOS LPC_FRAME# LPC frame indicates start of a new O 3.3V cycle or termination of a broken CMOS cycle.

  • Page 51: Lpc Bus Reference Schematics

    2.12.2 LPC Bus Reference Schematics 2.12.2.1 Super I/O Figure 19: LPC Super I/O Example (1) COM Express® Carrier Board Design Guide...
  • Page 52 Figure 19: LPC Super I/O Example (2) COM Express® Carrier Board Design Guide...

  • Page 53: Routing Considerations

    Figure 20: LPC Firmware Hub Please refer to: PICMG COM Express Carrier Board Design Guide Rev. 2.0 / December 6, 2013 Page 207 Figure 80 LPC Firmware Hub 2.12.3 Routing Considerations 2.12.3.1 General Signals LPC signals are similar to PCI signals. Route the LPC bus as 55 Ω, single-ended signals. The bus preferably should be referenced to ground, or to a well-bypassed power plane or a combination of the two.

  • Page 54: Serial Peripheral Interface Bus

    2.13 Serial Peripheral Interface Bus 2.13.1 Signal Definition Table 13: SPI Signal Definition Signal Pin Description SPI_CS# B97 Chip select for Carrier Board SPI – may be sourced O CMOS – from chipset SPI0 or SPI1 3.3V Suspend SPI_MISO A92 Data in to Module from Carrier SPI I CMOS –...

  • Page 55: Spi Reference Schematics

    2.13.2 SPI Reference Schematics Figure 21: SPI Reference Schematics 2.13.3 Routing Considerations The SPI signals SPI_MISO, SPI_MOSI, SPI_CS# and SPI_CLK should be routed with a maximum length of 4.5” and should match to each other within 0.1”. COM Express® Carrier Board Design Guide...

  • Page 56: General Purpose I2C Bus Interface

    2.14 General Purpose I2C Bus Interface 2.14.1 Signal Definitions Table 14: General Purpose I2C Interface Signal Descriptions Signal Description Power Rail I2C_CK General Purpose I2C Clock output I/O OD CMOS 3.3V Suspend I2C_DAT General Purpose I2C data I/O line. I/O OD CMOS 3.3V Suspend 2.14.2 Reference Schematics Figure 22: System Configuration EEPROM Circuitry...

  • Page 57: System Management Bus (Smbus)

    2.15 System Management Bus (SMBus) Figure 23: System Management Bus Separation COM Express® Carrier Board Design Guide...

  • Page 58: Signal Definitions

    2.15.1 Signal Definitions Table 15: System Management Bus Signals Signal Description Power Rail SMB_CK System Management Bus I/O OD CMOS 3.3V bidirectional clock line Suspend rail SMB_DAT System Management I/O OD CMOS 3.3V bidirectional data line. Suspend rail SMB_ALERT# B15 System Management Bus 3.3V I CMOS...

  • Page 59: General Purpose Serial Interface

    2.16 General Purpose Serial Interface 2.16.1 Signal Definitions Table 16: General Purpose Serial Interface Signal Definition Signal Description SER0_TX Transmit Line for Serial Port 0 O CMOS (protected) SER0_RX Receive Line for Serial Port 0 I CMOS (protected) SER1_TX A101 Transmit Line for Serial Port 1 (can be O CMOS (protected) shared with CAN function) SER1_RX...

  • Page 60: Reference Schematics

    2.16.2 Reference Schematics 2.16.2.1 General Purpose Serial Port Example Figure 24: General Purpose Serial Port Example (1) COM Express® Carrier Board Design Guide...
  • Page 61 Figure 24: General Purpose Serial Port Example (2) COM Express® Carrier Board Design Guide...

  • Page 62: Routing Considerations

    2.16.3 Routing Considerations There are no further routing considerations that need to be taken. 2.17 CAN Interface 2.17.1 Signal Definitions Table 17: CAN Interface Signal Definition Signal Description CAN_TX A101 Transmit Line for CAN (can be shared with O CMOS SER1 function) (protected) CAN_RX...

  • Page 63: Reference Schematics

    2.17.2 Reference Schematics Figure 25: CAN Bus Example (1) COM Express® Carrier Board Design Guide...

  • Page 64: Routing Considerations

    Figure 25: CAN Bus Example (2) 2.17.3 Routing Considerations It should be routed as a differential pair signal with 120 Ohm differential impedance. The end points of CAN bus should be terminated with 120 Ohms or with 60 Ohms from the CAN_H line and 60 Ohms from the CAN_L line to the CAN Bus reference voltage.

  • Page 65: Miscellaneous Signals

    2.18 Miscellaneous Signals Table 18: Miscellaneous Signals Signal Description Remarks TYPE0# The Type pins indicate the COM Express pin-out type of the O 5V Only Available on TYPE1# Module. To indicate the Module's pin-out type, the pins are T2-T6 TYPE2# either not connected or strapped to ground on the Module.

  • Page 66: Speaker Output

    2.18.1 Speaker Output Figure 26: Speaker Output Circuitry COM Express® Carrier Board Design Guide...

  • Page 67: Rtc Battery Implementation

    2.18.2 RTC Battery Implementation Figure 27: RTC Battery Circuitry with Serial Schottky Diode COM Express® Carrier Board Design Guide...

  • Page 68: Power Management Signals

    2.18.3 Power Management Signals Table 19: System States S0-S5 Definitions System State Description Power Rail State Full power on all power rails. All components are powered and the Full On system is fully functional. Full power on all power rails. In sleeping state, no system context is lost, Power-on Standby hardware maintains all system context.
  • Page 69 Table 20: Power Management Signal Descriptions Signal Pin Description Remarks PWRBTN# B12 Power button low active signal used to wake I 3.3V Drive with >=10mA Suspend up the system from S5 state (soft off). This CMOS signal is triggered on the falling edge. SYS_RESET# B49 Reset button input.
  • Page 70 Figure 28: PWRBTN# and SYS_RESET# Circuitry COM Express® Carrier Board Design Guide...

  • Page 71: Watchdog Timer

    2.18.4 Watchdog Timer Figure 29: Watchdog Timer Event Latch Schematic Please refer to: PICMG COM Express Carrier Board Design Guide Rev. 2.0 / December 6, 2013 Page 137 Figure 54: Watchdog Timer Event Latch Schematic 2.18.5 General Purpose Input/Output (GPIO) Table 21: GPIO Signal Definition Signal Pin Description...

  • Page 72: Fan Connector

    2.18.6 Fan Connector Figure 31: Fan Connector Reference Schematic COM Express® Carrier Board Design Guide...

  • Page 73: Thermal Interface

    2.18.7 Thermal Interface Table 22: Thermal Management Signal Descriptions Signal Pin Description THRM# B35 Thermal Alarm active low signal generated by the external I 3.3V hardware to indicate an over temperature situation. This signal CMOS can be used to initiate thermal throttling. THRMTRIP# A35 Thermal Trip indicates an overheating condition of the O 3.3V...

  • Page 74: Pci Bus

    2.19 PCI Bus 2.19.1 Signal Definitions Table 23: PCI Bus Signal Definition Signal Pin# Description Remarks PCI_AD0 PCI bus multiplexed address and data lines I/O 3.3V PCI_AD1 PCI bus multiplexed address and data lines I/O 3.3V PCI_AD2 PCI bus multiplexed address and data lines I/O 3.3V PCI_AD3 PCI bus multiplexed address and data lines...
  • Page 75 Signal Pin# Description Remarks PCI_STOP# PCI bus STOP control line, active low I/O 3.3V PCI_PAR PCI bus parity I/O 3.3V Parity Error: An external PCI device drivers PCI_PERR# I/O 3.3V PERR# by driving it low, when it receives data that has a parity error.

  • Page 76: Reference Schematics

    2.19.2 Reference Schematics 2.19.2.1 Resource Allocation Figure 32: PCI Bus Interrupt Routing Table 24: PCI Bus Interrupt Routing Device Signal Slot / Device 1 Slot / Device 2 Slot / Device 3 Slot / Device 4 IDSEL PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] INTA# PCI_IRQ[A]#...
  • Page 77 2.19.3.1 Device-Down Example Figure 33: PCI Device Down Example; Dual UART Please refer to: PICMG COM Express Carrier Board Design Guide Rev. 2.0 / December 6, 2013 Page 150 Figure 60: PCI Device Down Example; Dual UART COM Express® Carrier Board Design Guide...

  • Page 78: Ide And Compactflash (Pata)

    2.20 IDE and CompactFlash (PATA) 2.20.1 Signal Definitions Table 25: Parallel ATA Signal Descriptions Signal Description IDE40 IDE44 IDE_D0 Bidirectional data to / from IDE device. I/O 3.3V IDE_D1 Bidirectional data to / from IDE device. I/O 3.3V IDE_D2 Bidirectional data to / from IDE device. I/O 3.3V IDE_D3 Bidirectional data to / from IDE device.
  • Page 79 Figure 34: IDE 40 Pin and CompactFlash 50 Pin Connector Please refer to: PICMG COM Express Carrier Board Design Guide Rev. 2.0 / December 6, 2013 Page 155 Figure 63: IDE 40 Pin and CompactFlash 50 Pin Connector COM Express® Carrier Board Design Guide...

  • Page 80: Chapter 3 Power And Reset

    Chapter 3 Power and Reset The information provided in this chapter includes: COM Express® Carrier Board Design Guide...

  • Page 81: Atx Style Power Control

    3.1 ATX Style Power Control Reference Schematics Figure 35: AT and ATX Power Supply (1) COM Express® Carrier Board Design Guide...
  • Page 82 Table 26: ATX Signal Names ATX Signal Name Description Active-low, TTL-level input to ATX supply that, when low, enables all power rails. If high or PS_ON# floating, all ATX power rails are disabled except for the +5V Suspend rail. PWR_OK Active-high, TTL-level output signal from the ATX supply that indicates that the +12V, +5V, +3.3V and -12V outputs are all present and OK to use.
  • Page 83 Routing Considerations 3.3.1 VCC_12V and GND For the +12V power input (VCC_12V) to the Module, the trace should be wide enough to handle the maximum expected load. A power plane may be used for VCC_12V but is not recommended; VCC_12V should not be used as a reference for high-speed signals, such as PCIe, USB, or even PCI, because there may be switching noise present on VCC_12V.

  • Page 84: Chapter 4 Carrier Board Pcb Layout Guidelines

    Chapter 4 Carrier Board PCB Layout Guidelines COM Express® Carrier Board Design Guide...

  • Page 85: General

    4.1 General 4.2 PCB Stack-ups Note: 'Carrier Board PCB Layout Guidelines' assumes a thickness for the carrier PCB to be 0.0625 inches. Other PCB mechanics are possible but the described Stack-ups need to be adapted. 4.2.1 Four Layer Stack-up Figure 36: Four-Layer Stack-up The figure above is an example of a four layer stack-up.
  • Page 86 4.2.2 Six Layer Stack-up Figure 37: Six-Layer Stack-up The figure above is an example of a six layer stack-up. Layers L1, L3, L4 and L6 are used for signal-routing. Layers L2 and L5 are power and ground planes respectively. Microstrips on Layers 1 and 6 reference solid ground and power planes on Layers 2 and 5 respectively.
  • Page 87 4.2.3 Eight Layer Stack-up Figure 38: Eight-Layer Stack-up The figure above is an example of an eight layer stack-up. Layers L1, L3, L6 and L8 are used for signal-routing. Layers L2 and L7 are solid ground planes, while L4 and L5 are used for power.

  • Page 88: Trace Impedance Considerations

    4.3 Trace Impedance Considerations Figure 39: Stackup & Impedance COM Express® Carrier Board Design Guide...

  • Page 89: Chapter 5 Mechanical Considerations

    Chapter 5 Mechanical Considerations 5.1 Form Factors Figure 40: Mechanical comparison of available COM Express Form Factors All dimensions are shown in millimeters. COM Express® Carrier Board Design Guide...

  • Page 90: Heatspreader

    5.2 Heatspreader Figure 41: IBASE HSET976-1 Heatspreader Figure 42: Side View of Heatspreader, COM Express Module & Carrier board layer. COM Express® Carrier Board Design Guide...

  • Page 91: Com Express Carrier Board

    5.3 COM Express Carrier Board Figure 43: IBASE IP413 COM Express Carrier Board COM Express® Carrier Board Design Guide...

  • Page 92: Com Express Module And Heatsink

    5.4 COM Express Module and Heatsink Figure 44: IBASE ET976 and Heatsink COM Express® Carrier Board Design Guide...
  • Page 93 5.5 COM Express Connector (Tyco) Figure 45: Tyco 220-pin COM Express Connector (Pitch 0.5mm, H: 8mm) COM Express® Carrier Board Design Guide...

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