Sony SAT-W60 Service Manual page 15
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Also See for SAT-W60:
- Service manual (60 pages) ,
- User manual (55 pages) ,
- Installation manual (32 pages)
Table of Contents
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8
7
D
C P U _ E W R R D Y _ N
MISC_IO (10)
A U D _ V C C
A U D _ V C C
AUD_LINEIN_L
AUD_LINEIN_R
AUD_LINEOUT_L
C
AUD_LINEOUT_R
AUD_LINEOUT2_L
AUD_LINEOUT2_R
AUD_MIC_IN
A U D _ M O N O _ S W
A U D _ M O N O _ S W 2
AUD_MIC_SENSE
VID_COMP_IN
AUD_MIC_SEL_OUT_N
VID_COMP_IN
VID_Y_IN
SPD_SDATA
VID_Y_IN
VID_C_IN
VID_C_IN
SVID_IN_SENSE_N
VID_COMP_OUT
G P I O < 2 >
VID_COMP2_OUT
SVID_SENSE_N
VID_COMP2_IN
VID_COMP2_IN
AUD_LINEIN2_L
UART_CTS_N
AUD_LINEIN2_L
AUD_LINEIN2_R
U A R T _ D C D _ N
AUD_LINEIN2_R
UART_DTR_N
UART_CTS_DB9
UART_RTS_N
UART_CTS_DB9
UART_RTS_DB9
UART_RTS_DB9
U A R T _ R X D _ D B 9
U A R T _ R X D _ D B 9
UART_TXD_DB9
UART_TXD_DB9
B
S M C _ R E S E T _ N
SMC_INSERT_N
S M C _ P W R E N A B _ N
SC_CLKDIV<0>
SC_CLKDIV<1>
PIC_IR_CLK
IR_LED_SENSE
LED_DISP<0>
MODEM (6)
A
D A A _ H O O K S W _ N
DAA_LSTAT
D A A _ S N O O P _ N
DAA_RING_DET
M O D _ S M _ L R C L K
MOD_SM_BITCLK
M O D _ S M _ C L K
M O D _ S M _ X M T D A T
M O D _ S M _ R E C D A T
MOD_INT
M O D _ R E S E T
SYS_RESET_N
8
7
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6
CPU (3)
FUD_INT_N
CPU_AD<31..0>
CPU_CMD<8..0>
CPU_VALIDOUT_N
C P U _ M O D E C L K
C P U _ M O D E I N
C P U _ E X T R Q S T _ N
C P U _ R E L E A S E _ N
CPU_VALIDIN_N
C P U _ V C C O K
CPU_INT_N
C P U _ C R E S E T _ N
CPU_EVALI_N
C P U _ S R E S E T _ N
CPU_EVALI_N
C P U _ E V A L O _ N
C P U _ E V A L O _ N
C P U _ W R R D Y _ N
DIAG_INT_N
C P U _ E W R R D Y _ N
C P U _ C L K
P O W E R _ O K
SYS_RESET_N
AUD_LINEIN_L
AUD_LINEIN_R
AUD_BITCLK
AUD_LINEOUT_L
A U D _ C L K
AUD_LINEOUT_R
AUD_LRCLK
AUD_LINEOUT2_L
AUD_SDATA
AUD_LINEOUT2_R
AUD_SDATAIN
AUD_MIC_IN
SPD_SDATA
A U D _ M O N O _ S W
CPU_AD<31..0>
A U D _ M O N O _ S W 2
CPU_CMD<8..0>
AUD_MIC_SENSE
C P U _ C R E S E T _ N
AUD_MIC_SEL_OUT_N
CPU_INT_N
SPD_SDATA
C P U _ M O D E C L K
C P U _ M O D E I N
VID_COMP_OUT
C P U _ S R E S E T _ N
VID_COMP2_OUT
CPU_VALIN_N
VID_Y_OUT
C P U _ V A L O U T _ N
VID_Y_OUT
VID_C_OUT
CPU_EVALI_N
VID_C_OUT
G P I O < 9 >
C P U _ E V A L O _ N
C P U _ E W R R D Y _ N
UART_CTS_N
C P U _ V C C O K
U A R T _ D C D _ N
C P U _ W R R D Y _ N
UART_DTR_N
UART_RTS_N
UART_RXD
UART_RXD
UART_TXD
D A C _ C O M P A O U T
UART_TXD
D A C _ C R C B A O U T
S M C _ C L K
DAC_YAOUT
S M C _ C L K
SMC_DATA
SMC_DATA
S M C _ R E S E T _ N
SMC_INSERT_N
SMC_FIT
DIV_BCLK
SMC_FIT
S M C _ P E N _ N
DIV_DATA<7..0>
F U D _ G P I O < 6 >
DIV_HS
F U D _ G P I O < 7 >
DIV_LLC
DIV_LRCLK
A U D _ C L K
DIV_SDATA
PIC_CLK
IR_CLK
DIV_VS
GPIO<19..0>
IR_OUT
ID_DATA
IR_XMT
IR_IN
IIC_CLK
IR_REC
GPIO<15>
IIC_DATA
IR_CLK
MISC_LED<0>
IR_IN
IR_OUT
MC1_ADDR<10..0>
M C 1 _ B S
M C 1 _ C A S _ N
M C 1 _ C K E
MC1_CS_N<1..0>
MC1_DATA<31..0>
GPIO<14>
MC1_DQM<3..0>
G P I O < 4 >
M C 1 _ R A S _ N
G P I O < 5 >
M C 1 _ W E _ N
G P I O < 6 >
MC0_ADDR<10..0>
M C 0 _ B S
M O D _ L R C L K
M C 0 _ C A S _ N
MOD_BITCLK
M C 0 _ C K E
M O D _ C L K
MC0_CS_N<1..0>
M O D _ S D A T A
MC0_DATA<31..0>
MOD_SDATAIN
MC0_DQM<3..0>
M C 0 _ R A S _ N
RIO_DINT<0>
M C 0 _ W E _ N
GPIO<14>
SYS_5VRESET_N
DRAWING
TITLE=ELMER
A B B R E V = E L M E R
LAST_MODIFIED=Tue Mar 21 17:54:28 2000
6
5
5
4
FUD_INT_N
CPU_AD<31..0>
CPU_CMD<8..0>
C P U _ V A L O U T _ N
C P U _ M O D E C L K
C P U _ M O D E I N
CPU_EXTRQST_N
CPU_RELEASE_N
CPU_VALIN_N
C P U _ V C C O K
CPU_INT_N
C P U _ C R E S E T _ N
C P U _ S R E S E T _ N
RIO_ADDR<21..0>
ROM_ADDR<21..0>
C P U _ W R R D Y _ N
RIO_DATA<15..0>
ROM_DATA<15..0>
DIAG_INT_N
RIO_CE_N<3..2>
ROM_CE_N<3..2>
RIO_OE_N
R O M _ O E _ N
RIO_WE_N
R O M _ W E _ N
C P U _ C L K
S Y S _ P W R O K
SYS_RESET_N
R O M _ R E S E T _ N
SYS_RESET_N
MISC_LED<2..0>
AUD_BITCLK
MISC_LED<2..0>
MOD_BITCLK
A U D _ C L K
MOD_BITCLK
S O L O 2
M O D _ C L K
AUD_LRCLK
M O D _ C L K
M O D _ L R C L K
AUD_SDATA
M O D _ L R C L K
(2)
M O D _ S D A T A
AUD_SDATAIN
M O D _ S D A T A
MOD_SDATAIN
SPD_SDATA
MOD_SDATAIN
CPU_AD<31..0>
CPU_CMD<8..0>
C P U _ C R E S E T _ N
VID_PIXEL_CLK
CPU_INT_N
POT_CLK
P P _ A C K _ N
C P U _ M O D E C L K
P P _ A C K _ N
P P _ A U T O F D _ N
C P U _ M O D E I N
P P _ A U T O F D _ N
P P _ B U S Y
C P U _ S R E S E T _ N
P P _ B U S Y
PP_DATA<7..0>
CPU_VALIN_N
PP_DATA<7..0>
PP_DIR
C P U _ V A L O U T _ N
PP_DIR
P P _ E R R O R
CPU_EVALI_N
P P _ E R R O R
PP_FAULT_N
C P U _ E V A L O _ N
PP_FAULT_N
PP_INIT_N
C P U _ E W R R D Y _ N
PP_INIT_N
PP_SELECT
C P U _ V C C O K
PP_SELECT
PP_SELIN_N
C P U _ W R R D Y _ N
PP_SELIN_N
P P _ S T R O B E _ N
P P _ S T R O B E _ N
RIO_ADDR<21..0>
RIO_ADDR<21..0>
RIO_CE_N<3..0>
RIO_CE_N<3..0>
RIO_DATA<15..0>
D A C _ C O M P A O U T
RIO_DATA<15..0>
RIO_DEN_N<7..0>
D A C _ C R C B A O U T
RIO_DEN_N<7..0>
RIO_DEVIORDY
DAC_YAOUT
RIO_DEVIORDY
RIO_DINT<7..0>
RIO_DINT<7..0>
RIO_DRQ<1..0>
RIO_DRQ<1..0>
RIO_DAK_N<1..0>
RIO_DAK_N<1..0>
DIV_BCLK
RIO_OE_N
DIV_DATA<7..0>
RIO_OE_N
RIO_WE_N
DIV_HS
RIO_WE_N
S M C _ C L K
DIV_LLC
S M C _ C L K
SMC_DATA
DIV_LRCLK
SMC_DATA
SMC_FIT
DIV_SDATA
SMC_FIT
SMC_INSERT_N
DIV_VS
SMC_INSERT_N
S M C _ P E N _ N
GPIO<19..0>
S M C _ P E N _ N
S M C _ R E S E T _ N
ID_DATA
S M C _ R E S E T _ N
SYS_2XCLKIN
IIC_CLK
SYS_2XCLKIN
S Y S _ P W R O K
IIC_DATA
S Y S _ P W R O K
S Y S _ D P W R O K
IR_CLK
S Y S _ D P W R O K
SYS_RESET_N
IR_IN
SYS_RESET_N
SYS_5VRESET_N
IR_OUT
SYS_5VRESET_N
S Y S _ R S W T C H _ N
MC1_ADDR<10..0>
S Y S _ R S W T C H _ N
M C 1 _ B S
UART_CTS_N
M C 1 _ C A S _ N
UART_CTS_N
U A R T _ D C D _ N
M C 1 _ C K E
U A R T _ D C D _ N
UART_DTR_N
MC1_CS_N<1..0>
UART_DTR_N
UART_RTS_N
MC1_DATA<31..0>
UART_RTS_N
UART_RXD
MC1_DQM<3..0>
UART_RXD
UART_TXD
M C 1 _ R A S _ N
UART_TXD
VID_DATA<7..0>
M C 1 _ W E _ N
VID_DATA<7..0>
VID_HSYNC_N
MC0_ADDR<10..0>
VID_HSYNC_N
VID_VSYNC_N
M C 0 _ B S
VID_VSYNC_N
M C 0 _ C A S _ N
M C 0 _ C K E
MC0_CS_N<1..0>
MC0_DATA<31..0>
MC0_DQM<3..0>
M C 0 _ R A S _ N
This document contains privileged or otherwise legally protected
M C 0 _ W E _ N
information.
than the recipient is not authorized.
or otherwise use this document unless you are an authorized
representative of a named recipient.
$Id: body.1.1,v 1.6 1997/05/31 14:06:45 sleat Exp $
SET:
ENGINEER:
4
3
2
MEM (4)
M C 0 _ B S
M C 0 _ B S
MC0_ADDR<10..0>
MC0_ADDR<10..0>
MC0_DATA<31..0>
MC0_DATA<31..0>
M C 0 _ D Q M < 3 . . 0 >
MC0_DQM<3..0>
M C 0 _ R A S _ N
M C 0 _ R A S _ N
M C 0 _ C A S _ N
M C 0 _ C A S _ N
M C 0 _ W E _ N
M C 0 _ W E _ N
MC0_CS_N<1..0>
MC0_CS_N<1..0>
M C 0 _ C K E
M C 0 _ C K E
M C 1 _ B S
M C 1 _ B S
MC1_ADDR<10..0>
MC1_ADDR<10..0>
MC1_DATA<31..0>
MC1_DATA<31..0>
MC1_DQM<3..0>
ROM (5)
MC1_DQM<3..0>
M C 1 _ R A S _ N
M C 1 _ R A S _ N
M C 1 _ C A S _ N
M C 1 _ C A S _ N
M C 1 _ W E _ N
M C 1 _ W E _ N
MC1_CS_N<1..0>
MC1_CS_N<1..0>
M C 1 _ C K E
M C 1 _ C K E
MEM_CLK<3..0>
MEM_CLK<3..0>
AUDIO (8)
AUD_LINEIN2_L
AUD_LINEIN2_L
AUD_LINEIN2_R
AUD_LINEIN2_R
AUD_LINEIN_L
AUD_LINEIN_L
AUD_LINEIN_R
AUD_LINEIN_R
AUD_EXTIN_SEL
AUD_IN_SEL
AUD_LINEOUT_L
AUD_LINEOUT_L
AUD_LINEOUT_R
AUD_LINEOUT_R
AUD_LINEOUT2_L
AUD_LINEOUT2_L
AUD_LINEOUT2_R
AUD_LINEOUT2_R
AUD_MIC_IN
AUD_MIC_IN
A U D _ V C C
A U D _ R F U
RFU_AUDIO_OUT
AUD_TUNER_L
AUD_TUNER_L
A U D _ T U N E R _ R
A U D _ T U N E R _ R
A U D _ C L K
A U D _ C L K
AUD_BITCLK
AUD_BITCLK
AUD_LRCLK
AUD_LRCLK
AUD_INDATA
AUD_SDATAIN
AUD_OUTDATA
AUD_SDATA
AUD_MIC_SEL_OUT_N
AUD_MIC_SEL_OUT_N
A U D _ C C L K
GPIO<12>
AUD_CDATA
GPIO<13>
A U D _ C S _ N
GPIO<10>
A U D _ M U T E
GPIO<1>
AUD_MIC_SEL
G P I O < 3 >
A U D _ M O N O _ S W
A U D _ M O N O _ S W
A U D _ M O N O _ S W 2
A U D _ M O N O _ S W 2
SYS_RESET_N
SYS_RESET_N
VIDEO (7)
VID_DAC_Y
DAC_YAOUT
VID_DAC_C
D A C _ C R C B A O U T
VID_DAC_COMP
D A C _ C O M P A O U T
VID_Y_OUT
VID_Y_OUT
VID_C_OUT
VID_C_OUT
VID_COMP2_OUT
VID_COMP_OUT
VID_COMP_OUT
VID_COMP2_OUT
VID_COMP_RFU
VID_COMP_RFU
C WEBTV NETWORKS, INC. 1999
Disclosure of this information to anyone other
You may not read, copy,
E L M E R
TOP
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DATE:
SLEATOR/FULLER
APPROVED:
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REVISION:
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