Timing Diagram - Analog Devices dBCool ADT7476 Manual

Parameter
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
Input Low Voltage, V
IL
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
2
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU;DAT
Detect Clock Low Timeout, t
1
All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are T
accept input high voltages up to V
and V = 2.0 V for a rising edge.
IH
2
SMBus timing specifications are guaranteed by design and are not production tested.
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TIMING DIAGRAM

SCL
t
HD; STA
SDA
t
BUF
P S
TIMEOUT
, even when the device is operating down to V
MAX
t
R
t
LOW
t
HIGH
t
HD; DAT
Figure 2. Serial Bus Timing Diagram
Min Typ Max
0.8
−0.3
0.5
0.75 × V
0.4
±1
±1
5
10 400
50
4.7
4.7
4.0 50
1000
300
250
15 35
= 25°C and represent a most likely parametric norm. Logic inputs
A
. Timing specifications are tested at logic levels of V
MIN
t
F
t
SU; STA
t
SU; DAT
S
Rev. B | Page 5 of 72
Unit Test Conditions/Comments
V
V Minimum input voltage
V p-p
V
CC
V
μA V = V
IN CC
μA V = 0
IN
pF
See Figure 2
kHz
ns
μs
μs
μs
ns
μs
ns
ms Can be disabled
= 0.8 V for a falling edge,
IL
t
HD; STA
t
SU; STO
ADT7476
P