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5.4.4
Register 1m100: Status Register
Each status register bit has got its specific meaning. This is a read-only register.
29
Register Description
Bit Number
Status
0
1
2
3
4
5
6
7
13
Comment
0
The buffer configuration is invalid.
1
The buffer configuration is correct.
0
A station address has not been defined
yet.
1
The set station address is valid.
0
The PROFIBUS controller has not been
configured yet / it has not been configured
correctly.
1
Initialization has been successful.
0
The module has not been configured by
the PROFIBUS master yet.
1
The module is in the data exchange state,
i.e. communication with the master has
been established successfully.
1
The PROFIBUS master has sent a "read
data block" request.
1
The PROFIBUS master has sent a "write
data block" request.
1
Acyclic busy bit: Acyclic data are
exchanged between the module and the
PROFIBUS master; the acyclic data
cannot be accessed at the moment.
1
Acyclic error bit: Although bit 6 had been
set, an acyclic data range has been
accessed.
1
Busy bit: This bit indicates that the latest
action has not been completed by the
module yet. After reset, this bit will be set.
At the end of the initialization phase, it will
be reset again. The same applies to
command 5.
After writing the station address, this bit will
remain set, until the PROFIBUS controller
has been initialized completely.
0
no error
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