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1:1 Digital Interface Transceiver with PLL
DESCRIPTION
The WM8804 is a high performance consumer mode
S/PDIF transceiver with support for 1 received channel and
1 transmitted channel.
A crystal derived, or externally provided high quality master
clock is used to allow low jitter recovery of S/PDIF supplied
master clocks.
Generation of all typically used audio clocks is possible
using the high performance internal PLL. A dedicated
CLKOUT pin provides a high drive clock output.
A pass through option is provided which allows the device
simply to be used to clean up (de-jitter) the received digital
audio signals.
The device may be used under software control or stand
alone hardware control modes. In software control mode,
both 2-wire with read back and 3-wire interface modes are
supported.
Status and error monitoring is built-in and results can be
read back over the control interface, on the GPO pins or
streamed over the audio data interface in 'With Flags' mode
(audio data with status flags appended).
The audio data interface supports I
justified and DSP audio formats of 16-24 bit word length,
with sample rates from 32 to 192ks/s.
The device is supplied in a 20-lead Pb-free SSOP package.
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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FEATURES
•
S/PDIF (IEC60958-3) compliant.
•
Advanced jitter attenuating PLL with low intrinsic period
jitter of 50 ps RMS.
•
S/PDIF recovered clock using PLL, or stand alone crystal
derived clock generation.
•
Supports 10 – 27MHz crystal clock frequencies.
•
2-wire / 3-Wire serial or hardware control interface.
•
Programmable audio data interface modes:
2
-
I
S, Left, Right Justified or DSP
-
16/20/24 bit word lengths
•
1 channel receiver input and 1 channel transmit output.
•
Auto frequency detection / synchronisation.
•
Selectable output status data bits.
•
Up to 3 configurable GPO pins.
•
De-emphasis flag output.
•
Non-audio detection including DOLBY
•
Channel status changed flag.
•
Configurable clock distribution with selectable output
MCLK rate of 512fs, 256fs, 128fs and 64fs.
•
2.7 to 3.6V digital and PLL supply voltages.
•
20-lead SSOP package.
APPLICATIONS
•
AV processors and Hi-Fi systems
•
Music industry applications
•
DVD-P/DVD-RW
•
Digital TV
Production Data, September 2007, Rev 4.1
Copyright ©2007 Wolfson Microelectronics plc
WM8804
TM
TM
and DTS
.
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Summary of Contents for Wolfson WM8804
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Page 1: Description
1:1 Digital Interface Transceiver with PLL DESCRIPTION FEATURES • S/PDIF (IEC60958-3) compliant. The WM8804 is a high performance consumer mode • S/PDIF transceiver with support for 1 received channel and Advanced jitter attenuating PLL with low intrinsic period 1 transmitted channel. -
Page 2: Table Of Contents
WM8804 Production Data TABLE OF CONTENTS DESCRIPTION .......................1 FEATURES......................1 APPLICATIONS .....................1 BLOCK DIAGRAM ....................1 TABLE OF CONTENTS ..................2 PIN CONFIGURATION...................3 ORDERING INFORMATION ..................3 PIN DESCRIPTION ....................4 ABSOLUTE MAXIMUM RATINGS.................5 RECOMMENDED OPERATING CONDITIONS .............6 SUPPLY CURRENT ...................... 6 ELECTRICAL CHARACTERISTICS ..............6 MASTER CLOCK TIMING ..................... -
Page 3: Pin Configuration
WM8804 Production Data PIN CONFIGURATION ( Top View ) ORDERING INFORMATION TEMPERATURE MOISTURE PEAK SOLDERING DEVICE PACKAGE RANGE SENSITIVITY LEVEL TEMPERATURE 20-lead SSOP WM8804GEDS -25 to +85 MSL1 (Pb-free) 20-lead SSOP WM8804GEDS/R -25 to +85 MSL1 (Pb-free, tape and reel) -
Page 4: Pin Description
WM8804 Production Data PIN DESCRIPTION TYPE NAME DESCRIPTION SCLK Digital In/Out Control interface clock / GPO in hardware control mode. See note 2. GPO0 / SWIFMODE Digital In/Out General purpose digital output or selected functionality at hardware reset. See note 2. -
Page 5: Absolute Maximum Ratings
Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. -
Page 6: Recommended Operating Conditions
WM8804 Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS UNIT Digital supply range DVDD Ground DGND PLL supply range PVDD Ground PGND Notes: PLL and digital supplies must always be within 0.3V of each other. PLL and digital grounds must always be within 0.3V of each other. -
Page 7: Master Clock Timing
WM8804 Production Data MASTER CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 1 Slave Mode MCLK Timing Requirements Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T = +25 C, fs = 48kHz, MCLK = 256fs unless stated. -
Page 8: Digital Audio Interface - Slave Mode
WM8804 Production Data DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK LRCLK LRSU DOUT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T = +25 C, fs = 48kHz, MCLK = 256fs unless stated. -
Page 9: Control Interface - 3-Wire Mode
WM8804 Production Data CONTROL INTERFACE – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T = +25 C, fs = 48kHz, MCLK = 256fs unless stated. -
Page 10: Control Interface - 2-Wire Mode
WM8804 Production Data CONTROL INTERFACE – 2-WIRE MODE STHO STHO SDIN STSU STOP SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T = +25 C, fs = 48kHz, MCLK = 256fs unless stated. -
Page 11: Device Description
S/PDIF Block. For Consumer mode only the first 40-frames are used to make up the Channel and User blocks. Figure 6 illustrates the S/PDIF format. The WM8804 does not support transmission of user channel data. Received user channel data may be accessed via GPO pins. -
Page 12: Power Up Configuration
Figure 6 S/PDIF Format POWER UP CONFIGURATION The operating mode of the WM8804 is dependent upon the state of SDIN, SCLK, SDOUT, CSB and GPO0 when the device is powered up or a hardware reset occurs. Table 6 summarises the configuration options. - Page 13 WM8804 Production Data When the device powers up, all power up configuration pins are configured as inputs for a minimum of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based on 27MHz and 10MHz crystal clock frequencies respectively. This enables the pins to be sampled and the device to be configured before the pins are released to their selected operating conditions.
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Page 14: Control Interface Operation
Production Data CONTROL INTERFACE OPERATION Control of the WM8804 is implemented in either hardware control mode or software control mode. The method of control is determined by sampling the state of the SDIN/HWMODE pin at power up or at a hardware reset. If SDIN/HWMODE is low during power up the device is configured in hardware control mode, otherwise the device is configured in software control mode. - Page 15 WM8804 Production Data 3-WIRE SERIAL CONTROL MODE REGISTER READ-BACK Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status registers can be read. These status registers are labelled as “read only” in the Register Map section.
- Page 16 ‘W’ bit, MSB first). If the device address received matches the address of the WM8804, the WM8804 responds by driving SDIN low on the next clock pulse (ACK). This is a device acknowledgement of an address match. If the address does not match that of the WM8804, the device returns to the idle condition and waits for a new start condition and valid address.
- Page 17 The controller will issue the device address followed by a write bit, the register index will then be passed to the WM8804. At this point the controller will issue a repeated start condition and resend the device address along with a read bit. The WM8804 will acknowledge this and the WM8804 will become a slave transmitter.
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Page 18: Hardware Control Mode
MASTER / SLAVE MODE SELECTION The WM8804 can be configured in either master or slave mode. In software control mode this is set by writing to AIF_MS in the AIFRX register. In hardware control mode this is controlled by sampling the SCLK pin on power up or hardware reset. - Page 19 Production Data DIGITAL ROUTING CONTROL See page 20 for a full description of the signal routing options available in the WM8804. In Software control mode the value set in register TXSRC determines the S/PDIF transmitter data source. In hardware control mode the value of TXSRC can be set using the CSB pin.
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Page 20: Digital Routing Control
DIGITAL ROUTING CONTROL Figure 15 Digital Routing Paths within the WM8804 Digital signal routing within the WM8804 is controlled by the TXSRC register. In order to ensure proper operation when changing TXSRC, the S/PDIF transmitter module should be powered down prior to changing the TXSRC control register and powered up again once the routing path has been changed. -
Page 21: Master Clock And Phase Locked Loop
MASTER CLOCK AND PHASE LOCKED LOOP SOFTWARE MODE INTERNAL CLOCKING The WM8804 is equipped with a comprehensive clocking scheme that provides maximum flexibility and many configurable routing possibilities for the user in software mode. An overview of the software mode clocking scheme is shown in Figure 16. - Page 22 PLL as the PLL requires a jitter-free OSCCLK signal for optimum performance. PHASE-LOCKED LOOP (PLL) The WM8804 has an on-chip phase-locked loop (PLL) circuit that can be used to synthesise clock signals from the external oscillator clock. The PLL can be used to: •...
- Page 23 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PLL_K[7:0] 00100001 Fractional (K) part of PLL frequency ratio (R). PLL1 Value K is one 22-digit binary number spread over registers R3, PLL_K[15:8] 11111101 R4 and R5 as shown. PLL2 Note: PLL_K must be set to...
- Page 24 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PRESCALE PLL Pre-scale Divider Select PLL4 0 = Divide by 1 (PLL input clock = oscillator clock) 1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2) FREQMODE[1:0] PLL Post-scale Divider Select...
- Page 25 WM8804 Production Data PRE- PLL_N PLL_K FREQ MCLK MCLK CLKOUT SCALE MODE (MHz) (MHz) (Hex) (Hex) (MHz) [1:0] [1:0] (MHz) (MHz) 98.304 8.192 C49BA 24.576 49.152 98.304 8.192 C49BA 12.288 24.576 98.304 8.192 C49BA 6.144 12.288 98.304 8.192 C49BA 12.288 6.144...
- Page 26 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AIF_MS Audio Interface Mode Select AIFRX 0 = Slave mode – MCLK Input 1 = Master mode – MCLK Output Table 25 Audio Interface Mode Select When MCLK is configured as an output, the MCLK source and rate can be selected using the control bits shown in Table 26.
- Page 27 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS CLKOUTDIV[1:0] CLKOUT Divider Select PLL5 (Only valid when CLK1 is selected as CLKOUT output source) See for Table 27 CLKOUTDIV[1:0] configuration in PLL user mode. See Table 28 for CLKOUTDIV[1:0] configuration in PLL S/PDIF receive mode.
- Page 28 WM8804 Production Data The specified f frequencies that must be configured using the PLL_N and PLL_K register values for reception of specific S/PDIF sample rates are as follows: • Mode 1 (176.4/192kHz sample rate): f = 98.304MHz • Modes 2/3/4 (32/44.1/48/88.2/96kHz sample rates): f = 94.3104MHz...
- Page 29 WM8804 Production Data If indicated sample rate is 192kHz, then the user must know what the sampling frequency is (176.4kHz or 192kHz) since these cannot be distinguished. The user should then write appropriate calculated values (relative to oscillator frequency) to PRESCALE, PLL_N and PLL_K for 176.4/192kHz (mode 1) S/PDIF receiver sample...
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Page 30: Hardware Mode Internal Clocking
WM8804 Production Data HARDWARE MODE INTERNAL CLOCKING In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. An overview of the hardware mode clocking scheme is shown in Figure 17. -
Page 31: S/Pdif Transmitter
TXVAL_OVWR=1, where Validity is the value set in registers TXVAL_SF0 and TXVAL_SF1. USER DATA Set to 0 as User Data configuration is not supported in the WM8804 – if TXSRC=0 and TXSTATSRC =0 (S/PDIF receiver) User Data is set by the receiver. - Page 32 The Channel Status bits form a 192-frame block transmitted one bit per sub-frame. Each sub-frame forms its own 192-frame block. The WM8804 is a consumer mode device and only the first 40 bits of the block are used. All data transmitted from the WM8804 is stereo, so the channel status data is the same for both channels.
- Page 33 WM8804 Production Data REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS SRCNUM 19:16 0000 Source Number SPDTX3 [3:0] Refer to S/PDIF specification (IEC 60958-3) for full details. CHNUM1[1:0] 21:20 Channel Number for Subframe 1 CHNUM1 Channel Status Bits[21:20] Function Do not use channel number...
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Page 34: S/Pdif Receiver
WM8804 Production Data REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS MAXWL Maximum Audio Sample Word Length SPDTX5 0 = 20 bits 1 = 24 bits TXWL[2:0] 35:33 Audio Sample Word Length. Used with MAXWL to indicate Tx word length 000 = Word length not indicated... - Page 35 When the audio data sample is transferred to the AIF, and if the AIF is operating in a mode which has less data bits, then the WM8804 will reduce the audio data sample to the length of the AIF. For example, if the AIF is operating in 16 bit mode, but the SPDIF Rx receives an audio data sample length of 21 bits, then the WM8804 will reduce the 21 bits to 16 bits by removing the LSBs.
- Page 36 Use Of Channel Status Block RXCHAN1 0 = Consumer Mode 1 = Professional Mode (read-only) The WM8804 is a consumer mode device. Detection of professional mode may give erroneous behaviour. AUDIO_N Linear PCM Identification 0 = Data word represents audio PCM samples.
- Page 37 WM8804 Production Data REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS FREQ[3:0] 27:24 0001 Indicated Sampling Frequency RXCHAN4 Refer to S/PDIF specification (IEC 60958-3) for full details. CLKACU[1:0] 29:28 Clock Accuracy of Received Clock (read-only) 00 = Level II 01 = Level I...
- Page 38 WM8804 Production Data S/PDIF RECEIVER STATUS FLAGS There are several S/PDIF receiver status flags which are recorded by the WM8804. The flags are described in Table 45. These flags are available via GPIO pins or status registers. FLAG DESCRIPTION VISIBILITY...
- Page 39 Table 45 S/PDIF Receiver Status Flags Description ‘WITH FLAGS’ MODE The WM8804 features a ‘With Flags’ mode to enable the user to append status flags to the audio sample streamed transmitted from the digital audio interface. When WITHFLAG is set to 1 ‘With Flags’...
- Page 40 WM8804 Production Data INTERRUPT GENERATION The INT_N flag indicates that a change of status has occurred on one or more of the UNLOCK, INVALID, TRANS_ERR, CSUD, NON_AUDIO, CPY_N, REC_FREQ or DEEMPH status flags. To identify which flag caused the interrupt, the Interrupt Status Register (INTSTAT) must be read.
- Page 41 WM8804 Production Data Where the INT_N has been asserted by an update signal (UPD_NON_AUDIO, UPD_CPY_N, UPD_REC_FREQ, UPD_UNLOCK or UPD_DEEMPH) the S/PDIF Status Register (SPDSTAT) can be interrogated to establish the updated value of the flag. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS...
- Page 42 INT_N signal leaving the WM8804 to handle the error condition. If the TRANS_ERR and INVALID error flags are masked using the MASK register, the WM8804 output data from the S/PDIF Rx interface depends on the setting of FILLMODE. If FILLMODE=1, then the incoming data (which is errored) is overwritten with 0’s.
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Page 43: General Purpose Output (Gpo) Configuration
(UPD_NON_AUDIO). GENERAL PURPOSE OUTPUT (GPO) CONFIGURATION The WM8804 has a maximum of three configurable GPO pins depending upon the mode of operation of the device. By default GPO0 is available, however if 2-wire Software Control Mode is selected the CSB pin becomes GPO1 and the SDOUT pin becomes GPO2. -
Page 44: Digital Audio Interface
Production Data DIGITAL AUDIO INTERFACE Audio data is transferred to and from the WM8804 via the digital audio interface. Data from the digital audio interface transmitter may be passed to the S/PDIF transmitter or data from the S/PDIF receiver may be output on the digital audio interface receiver. The digital audio interface can be powered down using the AIFPD register bit described in Table 53. -
Page 45: Audio Data Formats
LEFT JUSTIFIED MODE In Left Justified mode, the MSB of DIN is sampled by the WM8804 on the first rising edge of BCLK following an LRCLK transition. The MSB of the output data (DOUT) changes on the same falling edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. - Page 46 Production Data RIGHT JUSTIFIED MODE In Right Justified Mode, the LSB of DIN is sampled by the WM8804 on the rising edge of BCLK preceding an LRCLK transition. The LSB of the output data (DOUT) changes on the falling edge of BCLK preceding an LRCLK transition, and may be sampled on the next rising edge of BCLK.
- Page 47 DSP MODE B In DSP Mode B, the MSB of the left channel data is sampled by the WM8804 on the first BCLK rising edge following a LRCLK rising edge. The right channel data follows the left channel data (Figure 22).
- Page 48 The following diagrams illustrate the position of the status flags within the audio sample for each audio data format when ‘With Flags’ Mode is enabled. ‘With Flags’ Mode is only available on pin DOUT. The WM8804 does not support Right Justified 24-Bit ‘With Flags’ Mode. Figure 23 Left Justified ‘With Flags’ Mode Figure 24 Right Justified ‘With Flags’...
- Page 49 WM8804 Production Data Figure 26 DSP Mode A ‘With Flags’ Figure 27 DSP Mode B ‘With Flags’ PD Rev 4.1 September 2007...
- Page 50 WM8804 Production Data AUDIO INTERFACE CONTROL The register bits controlling the audio interface are summarised below. Note that dynamically changing the audio data format may cause erroneous operation, and hence is not recommended. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS WITHFLAG ‘With Flags’ Mode Select SPDIFRX1 0: ‘With Flags’...
- Page 51 WM8804 Production Data Note 1: S/PDIF data frames contain a maximum of 24-bits of audio data. Note 2: In 24 bit I S mode, any data width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles (48 BCLK cycles).
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Page 52: Register Map
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8804 can be configured using the Control Interface. Any unused bits which are not specified should be set to ‘0’ . Not all registers can be read. - Page 53 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS Writing to this register will apply a reset to the device. RST/DEVID1 RESET Reading from this register will return the second part of the device ID 00000101 = 05h Reading from this register will return the first...
- Page 54 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS FREQMODE[1:0] PLL Post-scale Divider Select PLL5 Selects the PLL output divider value in conjunction with MCLKDIV and CLKOUTDIV. Refer to Table 23 for details of FREQMODE operation. Note: FREQMODE[1:0] bits are automatically set in S/PDIF Receive Mode.
- Page 55 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SPDIFINMODE S/PDIF Input Mode Select SPDMODE Selects the input circuit type for the receiver input. 0 = CMOS input 1 = Comparator input. Compatible with 500mVppAC coupled consumer S/PDIF input signals. Refer to S/PDIF specification (IEC 60958-3) for full details.
- Page 56 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS UNLOCK Update Signal UPD_UNLOCK INTSTAT 0 = INT_N not caused by a toggle of UNLOCK flag 1 = INT_N caused by a toggle of UNLOCK flag (read-only) INVALID Flag Interrupt Signal INT_INVALID...
- Page 57 Use Of Channel Status Block RXCHAN1 0 = Consumer Mode 1 = Professional Mode (read-only) The WM8804 is a consumer mode device. Detection of professional mode may give erroneous behaviour. AUDIO_N Linear PCM Identification 0 = Data word represents audio PCM samples.
- Page 58 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS CLKACU[1:0] Clock Accuracy of Received Clock (read-only) 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. MAXWL Maximum Audio Sample Word Length...
- Page 59 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SRCNUM 0000 Source Number SPDTX3 [3:0] Refer to S/PDIF specification (IEC 60958-3) for full details. CHNUM1[1:0] Channel Number for Subframe 1 CHNUM1 Channel Status Bits[21:20] Function Do not use channel number Send to Left Channel...
- Page 60 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS GPO0[3:0] 0000 Flags and Status bits available on GPO pins GPO0 0000 = INT_N 0001 = V 0010 = U 0011 = C 0100 = TRANS_ERR GPO1[3:0] 0111 0101 = SFRM_CLK GPO1...
- Page 61 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AIFRX_LRP Right, left and I S modes – LRCLK polarity and DSP mode select 1 = invert LRCLK polarity / DSP Mode B 0 = normal LRCLK polarity / DSP Mode A...
- Page 62 WM8804 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PLLPD PLL Powerdown PWRDN 0 = PLL enabled 1 = PLL disabled SPDIFRXPD S/PDIF Receiver Powerdown 0 = S/PDIF receiver enabled 1 = S/PDIF receiver disabled SPDIFTXPD S/PDIF Transmitter Powerdown 0 = S/PDIF transmitter enabled...
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Page 63: Applications Information
WM8804 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 28 Recommended External Components for Hardware Control Mode PD Rev 4.1 September 2007... - Page 64 WM8804 Production Data Figure 29 Recommended External Components for Software Control Mode PD Rev 4.1 September 2007...
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Page 65: Package Dimensions
WM8804 Production Data PACKAGE DIMENSIONS DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) DM0015.C GAUGE Θ PLANE 0.25 A A2 0.10 C SEATING PLANE Dimensions Symbols (mm) ----- ----- 0.05 ----- ----- 1.65 1.75 1.85 0.22 0.30 0.38 0.09... -
Page 66: Important Notice
Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
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