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19-5028; Rev 2; 6/10
6-Channel, Flash-Configurable System Manager
General Description
The MAX16067 flash-configurable system manager
monitors and sequences multiple system voltages. The
MAX16067 manages up to six system voltages simulta-
neously. The MAX16067 integrates an analog-to-digital
converter (ADC) and configurable outputs for sequenc-
ing power supplies. Device configuration information,
including overvoltage and undervoltage limits, time
delay settings, and the sequencing order is stored in
nonvolatile flash memory. During a fault condition, fault
flags and channel voltages can be automatically stored
in the nonvolatile flash memory for later readback.
The internal 1% accurate, 10-bit ADC measures each
input and compares the result to one overvoltage and
one undervoltage limit. A fault signal asserts when a
monitored voltage falls outside the set limits.
The MAX16067 supports a power-supply voltage of up to
14V and can be powered directly from the 12V interme-
diate bus in many systems.
The integrated sequencer provides precise control over
the power-up and power-down order of up to six power
supplies. Three outputs (EN_OUT1 to EN_OUT3) are
configurable with charge-pump outputs to directly drive
external n-channel MOSFETs.
The MAX16067 includes six programmable general-
purpose inputs/outputs (GPIOs). GPIOs are flash con-
figurable as a fault output, as a watchdog input or output,
or as a manual reset.
The MAX16067 features nonvolatile fault memory for
recording information during system shutdown events.
The fault logger records a failure in the internal flash
and sets a lock bit protecting the stored fault data from
accidental erasure.
An SMBus™ or a JTAG serial interface configures the
MAX16067. The MAX16067 is available in a 32-pin, 5mm
x 5mm, TQFN package and is fully specified over the
-40NC to +85NC extended temperature range.
PART
PIN-PACKAGE
MAX16067ETJ+
32 TQFN-EP*
Note: This device is specified over the -40NC to +85NC extended temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
SMBus is a trademark of Intel Corp.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
with Nonvolatile Fault Registers
S Operates from 2.8V to 14V
S 1% Accurate, 10-Bit ADC Monitors 6 Voltage
S Analog EN Monitoring Input
S 6 Monitored Inputs with Overvoltage and
S Nonvolatile Fault Event Logger
S Power-Up and Power-Down Sequencing
S 6 Outputs for Sequencing/Power-Good Indicators
S 3 Configurable Charge-Pump Outputs
S Six General-Purpose Inputs/Outputs Configurable
S SMBus and JTAG Interface
S Supports Cascading with MAX16065/MAX16066
S Flash-Configurable Time Delays and Thresholds
S -40NC to +85NC Extended Operating Temperature
Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
VOLTAGE-
DETECTOR INPUTS
6
Inputs
Undervoltage Limits
Capability
as:
Dedicated Fault Output
Watchdog Timer Function
Manual Reset
SMBus Alert
Fault Propagation Input/Output
Range
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/RAID Systems
Servers
GENERAL-PURPOSE
INPUTS/OUTPUTS
6
Features
Applications
SEqUENCING
OUTPUTS
6
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Related Manuals for Maxim MAX16067
Summary of Contents for Maxim MAX16067
- Page 1 Note: This device is specified over the -40NC to +85NC extended temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. SMBus is a trademark of Intel Corp. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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Page 2: Absolute Maximum Ratings
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four- layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. -
Page 3: Smbus Interface
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) = 2.8V to 14V, T = -40NC to +85NC, unless otherwise specified. Typical values are at V = 3.3V, = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS UNITS Differential Nonlinearity Monitoring all 6 inputs, no MON_ fault ADC Total Monitoring Cycle Time CYCLE... -
Page 4: Jtag Interface
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) = 2.8V to 14V, T = -40NC to +85NC, unless otherwise specified. Typical values are at V = 3.3V, = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS UNITS SMBus TIMING Serial-Clock Frequency Bus Free Time Between STOP and START Condition... - Page 5 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers SU:DAT SU:STA SU:STO HD:DAT HD:STA HIGH HD:STA START STOP START REPEATED START CONDITION CONDITION CONDITION CONDITION Figure 1. SMBus Timing Diagram TDI, TMS Figure 2. JTAG Timing Diagram _______________________________________________________________________________________...
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Page 6: Typical Operating Characteristics
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Typical Operating Characteristics (Typical values are at V = 3.3V, T = +25NC.) SUPPLY CURRENT NORMALIZED MON_THRESHOLD NORMALIZED EN THRESHOLD vs. V SUPPLY VOLTAGE vs. TEMPERATURE vs. TEMPERATURE 1.055 1.055 ABP AND DBP CONNECTED = +85°C TO V 1.040... - Page 7 -1.0 1000 1200 256 384 512 640 1024 (µA) (µA) CODE (LSB) SOURCE SOURCE FET TURN_ON WITH CHARGE PUMP DIFFERENTIAL NONLINEARITY vs. CODE MAX16067 toc13 EN_OUT1 5V/div -0.2 1A/div -0.4 -0.6 5V/div -0.8 -1.0 100ms/div 256 384 512 640 1024...
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Page 8: Pin Configuration
Nonvolatile Fault Registers Pin Configuration TOP VIEW 16 EN_OUT3 MON2 15 EN_OUT4 MON3 EN_OUT5 MON4 EN_OUT6 MON5 MAX16067 MON6 RESET GPIO1 GPIO2 TQFN *CONNECT EXPOSED PAD TO GND. Pin Description NAME FUNCTION GPIO3–GPIO6, General-Purpose Inputs/Outputs. Each GPIO_ can be configured to act as an input, a push-pull 1–4, 31, 32... -
Page 9: Functional Diagram
GPIO1 ALERT GPIO2 FAULT DECODE LOGIC GPIO3 TH_EN GPIO GPIO6 EXTFAULT CONTROL GPIO4 WATCHDOG GPIO5 MON1 TIMER MON2 EN_OUT1– MAX16067 EN_OUT6 SEQUENCER MON3 STATE VOLTAGE MACHINE MON4 SCALING RESET RESET OUTPUT MON5 LOGIC 10-BIT ADC DIGITAL (SAR) REGISTERS COMPARATORS MON6... -
Page 10: Detailed Description
5.079s. During a reverse sequence, slots are turned off which the device is ready for normal operation. RESET in reverse order starting from Slot 6. The MAX16067 can is asserted low up to the boot-up phase after which it be configured to power down in simultaneous mode or assumes its programmed active state. - Page 11 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Table 1. Current Sequencer Slot REGISTER BIT RANGE DESCRIPTION ADDRESS Current-sequencer state 0000 = Slot0 0001 = Slot1 0010 = Slot2 0011 = Slot3 [3:0] 0100 = Slot4 0101 = Slot5 0110 = Slot6 0111 = Power-on mode 1000 = Fault state 1001 to 1111 = Unused...
- Page 12 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Table 3. Power-Up/Power-Down Slot Delays Code Value − − × × × × × × µ 5 10 16 b 5 10 16 0 80 s 0000 0000 • • • • •...
- Page 13 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers SLOT 0 SLOT 1 SLOT 6 SLOT 2 FAULT SLOT1-SLOT2 DELAY SLOT1-SLOT2 EN_OUT1 DELAY BOTH ARE ASSIGNED TO SLOT 1 MON4 UV/OV MON4 MUST MONITORING BEGINS REACH UV WHEN MON4 THRESHOLD BY THIS REACHES UV TIME THRESHOLD...
- Page 14 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Table 5. MON_ and EN_OUT_ Assignment Registers REGISTER FLASH BIT RANGE DESCRIPTION ADDRESS ADDRESS [2:0] MON1 Not used 27Eh [6:4] MON2 Not used [2:0] MON3 Not used 27Fh [6:4] MON4 Not used [2:0] MON5 Not used...
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Page 15: Voltage Monitoring
Reverse Sequence Mode The two programmable thresholds for each monitored When the MAX16067 is fully powered up and EN is voltage include an overvoltage and an undervoltage pulled low or the software enable bit is set to ‘0’, the threshold. - Page 16 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Table 8. ADC Configuration Registers REGISTER ADDRESS FLASH ADDRESS BIT RANGE DESCRIPTION MON1 full-scale range 00 = 5.6V [1:0] 01 = 2.8V 10 = 1.4V 11 = Channel not converted MON2 full-scale range 00 = 5.6V [3:2] 01 = 2.8V...
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Page 17: General-Purpose Inputs/Outputs
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers General-Purpose Inputs/Outputs When GPIO1–GPIO6 are configured as general-purpose inputs/outputs, read values from the GPIO ports through GPIO1–GPIO6 are programmable general-purpose r1Eh and write values to GPIOs through r3Eh. Note that inputs/outputs. GPIO1–GPIO6 are configurable as a r3Eh has a corresponding flash register, which pro- manual reset input, a watchdog timer input and output, grams the default state of a general purpose output. - Page 18 Two configuration bits determine the behavior of the the Critical Faults section. Use r37h[7] to set the polarity MAX16067 when EXTFAULT is pulled low by an exter- of FAULT. nal device. Register bit r72h[5], if set to a ‘1’, causes...
- Page 19 The MAX16067 is capable of measuring overvoltage and undervoltage fault events. Fault conditions are The MAX16067 monitors the input (MON_) channels and detected at the end of each ADC conversion. An over- compares the results with an overvoltage threshold and voltage event occurs when the voltage at a monitored an undervoltage threshold.
- Page 20 Table 15). r1Ch[6] is set. Fault Flags The SMB Alert (ALERT) bit is set if the MAX16067 has Fault flags indicate the fault status of a particular input. asserted the SMBus Alert output. Clear by writing a ‘1’. The fault flag of any monitored input in the device can be See the SMBALERT (ALERT) section for more details.
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Page 21: Critical Faults
(see Table 17) for a fault condition voltage fault is detected during power-up/power-down to trigger a critical fault. and the MAX16067 enters to the fault state. Fault infor- Logged fault information is stored in flash registers mation can be stored to flash depending on r6D[1:0] r200h–r208h (see Table 18). - Page 22 MON6 ADC output (8 MSBs) Autoretry/Latch Mode autoretry delay from 20ms to 1.6s. See Table 19 for more The MAX16067 can be configured for one of two fault information on setting the autoretry delay. management methods: autoretry or latch-on-fault. Set When fault information is stored in flash (see the Critical r74h[4:3] to ‘00’...
- Page 23 (EN_OUT1–EN_OUT6) and EN_OUT3 act as high-voltage charge-pump out- puts to drive up to three external n-channel MOSFETs. The MAX16067 includes six programmable outputs. During sequencing, an EN_OUT_ output is configured These outputs are capable of connecting to either the as a charge-pump output 11V above GND. See the...
- Page 24 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Table 20. EN_OUT1–EN_OUT6 Configuration REGISTER FLASH BIT RANGE DESCRIPTION ADDRESS ADDRESS EN_OUT1 Configuration 00 = Active-low, open drain [1:0] 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull EN_OUT2 Configuration 00 = Active-low, open drain [3:2]...
- Page 25 1 = Assert EN_OUT1 1 = Assert EN_OUT2 1 = Assert EN_OUT3 234h 1 = Assert EN_OUT4 1 = Assert EN_OUT5 1 = Assert EN_OUT6 [7:6] Not used MAX16067 fig04 MAX16067 fig05 UVLO 2V/div 2V/div RESET RESET 2V/div 2V/div ASSERTED...
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Page 26: Reset Output
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Reset Output thresholds. Select the combination of MON_ inputs using r3Ch[5:0] and r3Dh[5:0]. Note that MON_ inputs con- The reset output, RESET, indicates the status of the figured as critical faults always cause RESET to assert sequencer and the monitored inputs. -
Page 27: Watchdog Timer
The watchdog timer operates together with or indepen- updates. Set r76h[6:4] to a value other than ‘000’ to dently of the MAX16067. When operating in dependent enable the watchdog startup delay. Set r76h[6:4] to ‘000’ mode, the watchdog is not activated until the sequenc- to disable the watchdog startup delay. - Page 28 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers the watchdog timer expires. RESET is not affected by exceeding UVLO and once the boot-up sequence is fin- the watchdog timer when the Watchdog Reset Output ished. When RESET is asserted by the sequencer state Enable bit (r76h[7]) is set to ‘0’.
- Page 29 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers < t < t < t WDI_STARTUP RESET 1µs Figure 8. Watchdog Startup Sequence with Watchdog Reset Output Enable Bit Set to ‘1’ Table 23. Watchdog Configuration REGISTER FLASH DESCRIPTION ADDRESS ADDRESS RANGE 1 = Independent mode 273h...
- Page 30 Early STOP Conditions A master device communicates to the MAX16067 by The MAX16067 recognizes a STOP condition at any point transmitting the proper address followed by command during transmission except if a STOP condition occurs in and/or data words. The slave address input, A0, is the same high pulse as a START condition.
- Page 31 A REPEATED START can be sent instead of a STOP the MAX16067, the device waits for the master device to condition to maintain control of the bus during a read generate an ACK.
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Page 32: Slave Address
Command Codes GND, DBP (or an external supply voltage greater than The MAX16067 uses eight command codes for block 2V), SCL, or SDA to set the device address on the bus. read, block write, and other commands. See Table 27 See Table 26 for a listing of all possible 7-bit addresses. - Page 33 The receive byte protocol allows the master device to address must be aligned to 8-byte boundaries—the 3 read the register content of the MAX16067 (see Figure LSBs of the initial address must be ‘000’. Write the 8 12). The flash or register address must be preset with bytes using a single block write command or using eight a send byte or write word protocol first.
- Page 34 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers To write a single byte, only the 8-bit memory address When PEC is enabled, the read byte protocol becomes: and a single 8-bit data byte are sent. The data byte is 1) The master sends a START condition. written to the addressed location if the memory address 2) The master sends the 7-bit slave ID plus a write bit is valid.
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Page 35: Block Read
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers 6) The master sends the 8-bit byte count (1 byte to 16 3) The addressed slave asserts an ACK on SDA. bytes), n. 4) The master sends 8 bits of the block read command 7) The addressed slave asserts an ACK on SDA. - Page 36 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers SEND BYTE FORMAT RECEIVE BYTE FORMAT ADDRESS R/W ACK COMMAND ADDRESS R/W ACK DATA NACK P 7 BITS 8 BITS 7 BITS 8 BITS SLAVE ADDRESS: Address DATA BYTE: Presets the internal SLAVE ADDRESS: Address DATA BYTE: Data is read from of the slave on the serial...
- Page 37 09h as the slave address. to run at a time. The MAX16067 contains extra JTAG The slave acknowledges the ARA (09h) address and instructions and registers not included in the JTAG sends its own SMBus address to the master.
- Page 38 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Test Access Port (TAP) instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test Controller State Machine data register remains at its current value. On the rising The TAP controller is a finite state machine that responds edge of TCK, the controller goes to the shift-DR state if to the logic level at TMS on the rising edge of TCK.
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Page 39: Instruction Register
Table 28 shows the instructions supported by the MAX16067 and the respective opera- Exit1-IR: A rising edge on TCK with TMS low puts the tional binary codes. - Page 40 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers BYPASS: When the BYPASS instruction is latched into memory in the MAX16067. When the LOAD ADDRESS the instruction register, TDI connects to TDO through the instruction latches into the instruction register, TDI con- 1-bit bypass test data register.
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Page 41: Applications Information
U The MAX16067 needs to be powered from an inter- Restrictions When Writing to Flash mediate voltage bus or auxiliary voltage supply so Flash must be written to 8 bytes at a time. The initial programming can occur even when the board’s power... -
Page 42: Configuring The Device
Approximate the slew a Fault Condition rate, SR, using the following formula: Power to the MAX16067 must be maintained for a spe- SR = I GATE cific period of time to ensure a successful flash fault log... - Page 43 RESET outputs as a power-good signal. to GND. Bypass V with a 10FF capacitor to ground. U For a large number of voltage rails, the MAX16067 Avoid routing digital return currents through a sensitive can be cascaded hierarchically by using one master analog area, such as an analog supply input return path device’s EN_OUT_s to control the EN inputs of several...
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Page 44: Register Map
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Register Map FLASH REGISTER READ/ DESCRIPTION ADDRESS ADDRESS WRITE ADC VALUES, FAULT REGISTERS, GPIOs AS INPUT PORTS—NOT IN FLASH — MON1 ADC output, MSBs — MON1 ADC output, LSBs — MON2 ADC output, MSBs —... - Page 45 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Register Map (continued) FLASH REGISTER READ/ DESCRIPTION ADDRESS ADDRESS WRITE ADC—CONVERSIONS ADCs voltage ranges for MON_ monitoring ADCs voltage ranges for MON_ monitoring 245–247 045–047 — Reserved INPUT THRESHOLDS — Reserved MON1 OV threshold MON1 UV threshold —...
- Page 46 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers Register Map (continued) FLASH REGISTER READ/ DESCRIPTION ADDRESS ADDRESS WRITE TIMEOUTS Watchdog independent mode, margin enabled, soft RESET functionality ADC fault deglitch/autoretry configuration WDI toggle/fault timeout, reverse sequencing bit WDRESET, WD timers Sequence delay for Slot 0 Sequence delay for Slot 1 Sequence delay for Slot 2...
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Page 47: Package Information
Chip Information PROCESS: BiCMOS For the latest package outline information and land pat- terns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suf- fix character, but the drawing pertains to the package regardless of RoHS status. -
Page 48: Revision History
Register Map table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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