Denon DRA-N5 Service Manual page 67

Physical Characteristics
Terminal Assignments
TAS5508C (AMP : IC108)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VRA_PLL
1
PLL_FLT_RET
2
PLL_FLTM 3
PLL_FLTP
4
AVSS
5
AVSS
6
VRD_PLL
7
AVSS_PLL
8
AVDD_PLL 9
VBGAP 10
RESET
11
HP_SEL
12
PDN
13
MUTE
14
DVDD 15
DVSS 16
17
TAS5508
8-Channel Digital Audio PWM Processor
SLES091C – FEBRUARY 2004 – REVISED AUGUST 2005
2.1.3
Ordering Information
TAS5508 Pin Discriptions
T
A
0°C to 70°C
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure
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PAG PACKAGE
(TOP VIEW)
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Terminal Descriptions
TERMINAL
5-V
TYPE (1)
TOLERANT
NAME NO.
AVDD_PLL 9 P
AVSS 5, 6 P
AVSS_PLL 8 P
BKND_ERR 37 DI
DVDD 15, 36 P
DVDD_PWM 54 P
DVSS 16, 34, P
35, 38
DVSS_PWM 53 P
HP_SEL 12 DI 5 V
LRCLK 26 DI 5 V
MCLK 63 DI 5 V
MUTE 14 DI 5 V
OSC_CAP 18 AO
PDN 13 DI 5 V
PLL_FLT_RET 2 AO
PLL_FLTM 3 AO
PLL_FLTP 4 AI
PSVC 32 O
PWM_HPML 59 DO
PWM_HPMR 61 DO
PWM_HPPL 60 DO
PWM_HPPR 62 DO
PWM_M_1 40 DO
PWM_M_2 42 DO
PWM_M_3 44 DO
PWM_M_4 46 DO
PWM_M_5 55 DO
PWM_M_6 57 DO
PWM_M_7 49 DO
PWM_M_8 51 DO
PWM_P_1 41 DO
PWM_P_2 43 DO
proper input logic levels if the terminals are left unconnected (pullups => logic-1 input; pulldowns => logic-0 input). Devices that drive
inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 200 mA, while maintaining a logic-1 drive level.
Description
VR_PWM
48
PWM_P_4
47
46 PWM_M_4
PWM_P_3
45
PWM_M_3
44
PWM_P_2
43
PWM_M_2
42
PWM_P_1
41
40 PWM_M_1
39 VALID
DVSS
38
BKND_ERR
37
DVDD
36
35 DVSS
34 DVSS
33 VR_DIG
P0010-01
PLASTIC 64-PIN PQFP (PN)
TERMINATION (2)
TAS5508PAG
3.3-V analog power supply for PLL. This terminal can be connected to the same
power source used to drive power terminal DVDD, but to achieve low PLL jitter,
this terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR
capacitor.
Analog ground
Analog ground for PLL. This terminal should reference the same ground as
terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must
be minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground-distribution techniques to achieve a quiet ground reference
at this terminal.
Pullup Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to any system parameters, with
all H-bridge drive signals going to a hard-mute (M) state.
3.3-V digital power supply
3.3-V digital power supply for PWM
Digital ground
Description
Digital ground for PWM
Pullup Headphone in/out selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
Serial-audio data left/right clock (sampling-rate clock)
Pulldown MCLK is a 3.3-V master clock input. The input frequency of this clock can range
from 4 MHz to 50 MHz.
Pullup Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
Oscillator capacitor
Pullup Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The internal parameters are preserved through
a power-down cycle, as long as RESET is not active. The duration for system
recovery from power down is 100 ms.
PLL external filter return
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL positive input. Connected to PLL_FLT_RTN via an RC network
Power-supply volume control PWM output
PWM left-channel headphone (differential –)
PWM right-channel headphone (differential –)
PWM left-channel headphone (differential +)
PWM right-channel headphone (differential +)
PWM 1 output (differential –)
PWM 2 output (differential –)
PWM 3 output (differential –)
PWM 4 output (differential –)
PWM 5 output (differential –)
PWM 6 output (differential –)
PWM 7 (lineout L) output (differential –)
PWM 8 (lineout R) output (differential –)
PWM 1 output (differential +)
PWM 2 output (differential +)
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DESCRIPTION
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