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Efinix Titanium User Manual

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Titanium Interfaces
User Guide
UG-TiINTF-v2.0
February 2022
www.efinixinc.com
Copyright
2022. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other
©
trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.

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  • Page 1 Copyright 2022. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other © trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.

  • Page 2: Table Of Contents

    Titanium Interfaces User Guide Contents About the Interface Designer......................iv Chapter 1: Get Oriented........................5 Interface Blocks............................7 Package/Interface Support Matrix......................8 Interface Block Connectivity........................8 Designing an Interface..........................9 Create or Delete a Block........................10 Using the Resource Assigner........................ 11 Resource View..........................12 Importing and Exporting Assignments..................13 Interface Designer Output Files......................15...
  • Page 3 Titanium Interfaces User Guide Create an LVDS RX Interface.........................77 Design Check: LVDS Errors and Warnings..................78 Chapter 7: HyperRAM Interface....................86 About the HyperRAM..........................86 Using the HyperRAM Interface......................87 Chapter 8: JTAG User TAP Interface..................... 89 JTAG Mode.............................. 89 Using the JTAG User TAP Block......................92 Design Check: JTAG User Tap Errors and Warnings.................

  • Page 4: About The Interface Designer

    Titanium Interfaces User Guide About the Interface Designer Titanium FPGAs wrap a Quantum -accelerated core with a periphery that sends signals ™ out to the device pins. The core contains the logic, embedded memory, and multipliers. The device periphery includes blocks such as GPIO pins, LVDS, MIPI, DDR, and PLLs.

  • Page 5: Chapter 1: Get Oriented

    Titanium Interfaces User Guide Chapter 1 Get Oriented Contents: Interface Blocks • • Package/Interface Support Matrix • Interface Block Connectivity • Designing an Interface Create or Delete a Block • Using the Resource Assigner • • Interface Designer Output Files •...
  • Page 6 Titanium Interfaces User Guide Figure 2: Interface Designer When you first open the Interface Designer for your project, the Design Explorer shows the Device Settings folder (with default settings) and empty folders for the interface blocks your chosen device supports. You need to add blocks as required for your design.

  • Page 7: Interface Blocks

    Titanium Interfaces User Guide Interface Blocks Titanium FPGAs support a variety of interface blocks. The available blocks differ depending on which FPGA you target. You need to assign a resource for every block you use. The following table describes the interface blocks supported in the Efinity software version ®...

  • Page 8: Package/Interface Support Matrix

    Package/Interface Support Matrix Some interfaces are only available in certain packages. The following table describes which interfaces are supported in specific FPGA/package combinations for the Efinity software ® v2021.2. Table 2: Titanium Interface/Package Combinations Supported in Efinity Software ® v2021.2 Package Ti35...

  • Page 9: Designing An Interface

    When designing for Titanium FPGAs, you create an RTL design for the core and also configure the interface blocks. From the perspective of the core, outputs from the core are inputs to the interface block and inputs to the core are outputs from the interface block.

  • Page 10: Create Or Delete A Block

    Titanium Interfaces User Guide During the design process, you can generate reports, which are available in the Efinity ® Results tab. When you generate reports, the software also saves your design. Use the design checker to check the interface for errors and to ensure that your settings are valid.

  • Page 11: Using The Resource Assigner

    4. Press Enter. Note: Titanium: When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO pins in the same bank. This separation reduces noise. The Efinity software issues an error if you do not leave this separation.

  • Page 12: Resource View

    Titanium Interfaces User Guide Figure 4: Resource Assigner Resource View When assigning GPIO, sometimes you want to know which resource can be used as a global clock, global control, or other special function. You can look it up in the pin table for the FPGA and package you are targeting, but an easier way is to use the Resource View in the Resource Assigner.

  • Page 13: Importing And Exporting Assignments

    • Replaces instances you renamed with the new name Learn more: For help understanding messages, refer to the "Design Check" topics in the Titanium Interfaces User Guide. These topics describe the messages the Interface Designer generates and gives suggestions on how to fix errors and warnings.
  • Page 14 Titanium Interfaces User Guide # Package: 81-ball FBGA (final) # Project: pt_demo # Configuration mode: active (x1) # Timing Model: C2 (final) # Create instance design.create_output_gpio("Fled",3,0) design.create_inout_gpio("Sled",3,0) design.create_output_gpio("Oled",3,0) design.create_clockout_gpio("Oclk_out") design.create_pll_input_clock_gpio("pll_clkin") design.create_global_control_gpio("resetn") # Set property, non-defaults design.set_property("Fled","OUT_REG","REG") design.set_property("Fled","OUT_CLK_PIN","Fclk") design.set_property("Sled[0]","IN_PIN","") design.set_property("Sled[0]","OUT_PIN","Sled[0]") design.set_property("Sled[1]","IN_PIN","") design.set_property("Sled[1]","OUT_PIN","Sled[1]")

  • Page 15: Interface Designer Output Files

    • <project name>.pinout.rpt—Has the board design pinout in a nicely formatted text file • format. <project name>.pt_timing.rpt—Timing report for the Titanium interface logic. • <project name>.pt.sdc—Template SDC file to constrain the FPGA design pins based • on the interface configuration.
  • Page 16 Titanium Interfaces User Guide Learn more: For more information on using the Python API to script an interface, refer to the Efinity Interface Designer Python API. www.efinixinc.com...

  • Page 17: Chapter 2: Device Settings

    However, in many situations the safest course of action is to assume that the FPGA's behavior is corrupted until it is reconfigured. Titanium FPGAs contain built-in circuitry to help detect SEUs. This circuitry periodically monitors the FPGA's CRAM, detects if a CRAM value has changed from the programmed state, and sends status signals to user logic.

  • Page 18: Enable Seu Detection

    User Logic Titanium FPGAs can monitor the CRAM while the FPGA is operating normally in user mode; When the SEU detection circuitry is triggered, it calculates a 32-bit CRC value based on CRAM values and compares it to a CRC computed by the Efinity software and stored in the configuration bitstream.

  • Page 19: Seu Detection Circuitry

    Titanium Interfaces User Guide SEU Detection Circuitry Your user logic connects to the SEU detection circuitry using the following pins. Table 4: SEU Detection Pins GUI Option Default Signal Name Direction Description SEU Start Detection Pin seu_START Input Manual mode only. To use this pin to initiate an...

  • Page 20: Design Check: Configuration Messages

    Titanium Interfaces User Guide Design Check: Configuration Messages When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

  • Page 21: I/O Banks Interface

    Titanium I/O Banks Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has independent power pins. The number and voltages supported vary by FPGA and package. Table 5: Titanium I/O Banks by FPGA and Package Package I/O Banks...

  • Page 22: Dynamic Voltage Support

    Titanium Interfaces User Guide Dynamic Voltage Support Titanium HVIO I/O banks support dynamic voltage shifting. This feature lets you change the voltage to the I/O bank during user mode. There are two methods for changing the voltage: • If you are not using 1.8 V at all, you can simply change the voltage at any time. For example, you can change from 3.3 V to 2.5 V and then back to 3.3 V.

  • Page 23: Design Check: I/O Bank Messages

    Titanium Interfaces User Guide Design Check: I/O Bank Messages When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.

  • Page 24: Chapter 3: Clock And Control Networks

    Titanium Interfaces User Guide Chapter 3 Clock and Control Networks Contents: Clock Sources that Drive the Global and Regional Networks • • Configuring the Dynamic Clock Multiplexers • Driving both the Global and Regional Networks • Design Check: Clock Control Messages The clock and control network is distributed through the FPGA to provide clocking for the core's LEs, memory, DSP blocks, I/O blocks, and control signals.
  • Page 25 Titanium Interfaces User Guide Figure 10: Global and Regional Clock Network Overview (Ti90, Ti120, Ti180) Global Signals Regional Signals Interface Only Region Core and Interface Regions Regions for Interface Only Region Global Signals Core and Interface Regional Signals GBUF RBUF Note: For detailed descriptions of the clock networks, refer to the data sheet.

  • Page 26: Clock Sources That Drive The Global And Regional Networks

    Clock Sources that Drive the Global and Regional Networks The Titanium global and regional networks are highly flexible and configurable. Clock sources can come from interface blocks, such as GPIO or PLLs, or from the core fabric. Note: For more information on the clock sources that can drive the global and regional networks, refer to the data sheet.

  • Page 27: Configuring The Dynamic Clock Multiplexers

    Titanium Interfaces User Guide Configuring the Dynamic Clock Multiplexers You configure the dynamic clock multiplexers in the Interface Designer. Expand Device Setting > Clock/Control Configuration and then click the multiplexer for the bottom, left, right, or top. Table 7: Global Buffer Configuration...

  • Page 28: Design Check: Clock Control Messages

    Titanium Interfaces User Guide Design Check: Clock Control Messages When you check your design, the Interface Designer applies design rules to your clock and control settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.
  • Page 29 Titanium Interfaces User Guide clkmux_rule_clocks_routed (error) Message Unrouted pins driving inputs of clock mux <ins name>:<inputs not routeable> To fix The software tries to route all of the clocks according to the scheme shown in "Driving the Global Network" in the data sheet. If it cannot find a mapping, it issues this error. Reassign the instances to other resources or try using a different PLL output clock (if they are not all are assigned).
  • Page 30 Titanium Interfaces User Guide clkmux_rule_global_regional_resource (error) Message Regional buffer resource <name> does not support global connection To fix Some clock sources cannot connect to the global network, e.g., PLL CLKOUT4. Look in the Resource Assigner Alt Conn column to find a different resource that can connect.

  • Page 31: Chapter 4: Ddr Interface

    About the DDR DRAM Interface • • DDR Interface Designer Settings Some Titanium FPGAs have a hardened IP interface block to communicate with off-the-shelf memories. Refer to the Package/Interface Support Matrix on page 8 to find out if your FPGA supports DDR.
  • Page 32 Titanium Interfaces User Guide Figure 11: DDR DRAM Interface Block Diagram FPGA Core PHY and AXI Block Signals Reference Clock Block Reference Clock GPIO Block(s) Note: The PLL reference clock must be driven by I/O pads. The Efinity software issues ®...
  • Page 33 Titanium Interfaces User Guide Table 11: Register Configuration Signals Signal Direction Clock Domain Description CR_ACLK Input AXI Control Register Clock. CR_ARESETN Input CR_CLK Register Reset (active low). CR_ARADDR[14:0] Input CR_CLK Register Read Command Address. CR_ARID[5:0] Input CR_CLK Register Read Command ID.
  • Page 34 Titanium Interfaces User Guide Table 12: Controller Signals Signal Direction Clock Domain Description CTRL_CLK Input Clock to controller. CTRL_RSTN Input CTRL_CLK Active low controller reset. CTRL_INT Output Controller detects Interrupt. CTRL_MEM_RST_VALID Output Controller has reseted. CTRL_REFRESH Output CTRL_CLK Indicate controller is executing refresh command.
  • Page 35 Titanium Interfaces User Guide Table 16: AXI4 Write Response Channel Signals (Interface to FPGA Fabric) Signal Direction Clock Description Domain x is 0 or 1 BID_x[5:0] Output ACLK_x Response ID tag. This signal is the ID tag of the write response.
  • Page 36 Titanium Interfaces User Guide Table 19: AXI4 Read Address Signals (Interface to FPGA Fabric) Signal Direction Clock Description Domain x is 0 or 1 ARADDR_x[31:0] Input ACLK_x Read address. It gives the address of the first transfer in a burst transaction.

  • Page 37: Ddr Interface Designer Settings

    Titanium Interfaces User Guide DDR Interface Designer Settings The following tables describe the settings for the Titanium DDR block in the Interface Designer. Table 21: Base Tab Parameter Choices Notes Instance Name User defined Indicate the DDR instance name. This name is the prefix for all DDR signals.
  • Page 38 Read Address Channel tab User defined These tabs defines the AXI signal names for the channels. Efinix recommends that you Write Address Channel tab use the default names. Write Response Channel tab Read Data Channel tab Write Data Channel tab www.efinixinc.com...

  • Page 39: Chapter 5: Gpio Interface

    ® input, output, or bi-directional pin in your design. Titanium GPIO pins have various features, depending on the position of the pin and which package you are using. Refer to the Resource Assigner in the Interface Designer for the features of the GPIO pin you want to use.
  • Page 40 LVCMOS 1.8 V GPIO Important: Efinix recommends that you limit the number of 3.0/3.3 V HVIO as I/O or output to 6 per bank to avoid switching noise. The Efinity software issues a warning if you exceed the recommended limit.

  • Page 41: Features For Hvio And Hsio Configured As Gpio

    Titanium Interfaces User Guide Features for HVIO and HSIO Configured as GPIO The following table describes the features supported by HVIO and HSIO configured as GPIO. Table 28: Features for HVIO and HSIO Configured as GPIO Feature HVIO HSIO Configured...

  • Page 42: Double-Data I/O

    Titanium Interfaces User Guide Double-Data I/O Titanium FPGAs support double data I/O (DDIO) on input and output registers. In this mode, the DDIO register captures data on both positive and negative clock edges. The core receives 2 bit wide data from the interface.

  • Page 43: Programmable Delay Chains

    Titanium Interfaces User Guide Programmable Delay Chains The HSIO configured as GPIO supports programmable delay chain. In some cases you can use static and dynamic delays at the same time. Table 30: Programmable Delay Support Delay Type GPIO Type Description...

  • Page 44: About The Hvio Interface

    Titanium Interfaces User Guide About the HVIO Interface The HVIOs are grouped into banks. Each bank has its own VCCIO33 that sets the bank voltage for the I/O standard. Each HVIO consists of I/O logic and an I/O buffer. I/O logic connects the core logic to the I/O buffers.
  • Page 45 Titanium Interfaces User Guide Table 31: HVIO Signals (Interface to FPGA Fabric) Signal Direction Description IN[1:0] Output Input data from the HVIO pad to the core fabric. IN0 is the normal input to the core. In DDIO mode, IN0 is the data captured...

  • Page 46: About The Hsio Interface

    Titanium Interfaces User Guide About the HSIO Interface Each HSIO block uses a pair of I/O pins as one of the following: • Single-ended HSIO—Two single-ended I/O pins (LVCMOS, SSTL, HSTL) • Differential HSIO—One differential I/O pins: — Differential SSTL and HSTL —...

  • Page 47: Hsio Configured As Gpio

    Titanium Interfaces User Guide HSIO Configured as GPIO You can configure each HSIO block as two GPIO (single-ended) or one GPIO (differential). Figure 16: I/O Interface Block HSIO Block Configured as GPIO I/O Logic Buffer Buffer INCLK Deserializer Pull-Up Resistor...
  • Page 48 Titanium Interfaces User Guide Table 33: HSIO Block Configured as GPIO Signals (Interface to FPGA Fabric) Signal Direction Description IN[3:0] Output Input data from the pad to the core fabric. IN0 is the normal input to the core. In DDIO mode, IN0 is the data captured...
  • Page 49 Titanium Interfaces User Guide Figure 17: I/O Buffer Path for LVCMOS OE P HSIO Buffer Buffer Out P Buffer In P VREF OE N Buffer Out N Buffer In N VREF When using an HSIO with the HSTL or SSTL I/O standards, you must configure an I/O pad of the standard's input path as a VREF pin.

  • Page 50: Using The Gpio Block

    Titanium Interfaces User Guide When using an HSIO with the differential HSTL or differential SSTL standard, you must use both GPIO resources in the HSIO. You use the core interface pins associated with the P resource. Figure 19: I/O Buffer Path for Differential HSTL and SSTL...
  • Page 51 Titanium Interfaces User Guide Input Mode Use input mode for input signals. Table 35: Input Mode Options Option Choices Description Connection Type normal, gclk, gctrl, Some pins have alternate functions, and you use this option to pll_clkin, pll_extfb, choose the function. (This option only applies to pins that have mipi_clkin, rclk, rctrl, alternate functions.
  • Page 52 Titanium Interfaces User Guide Option Choices Description Enable Dynamic On or off For inputs, 64 steps with approximately 25 ps of delay per step. If Delay you enable this option, specify the enable, reset, and control pins as well as the clock pin.

  • Page 53: Using The Gpio Bus Block

    Titanium Interfaces User Guide Inout mode also has an output enable signal (optionally registered) to enable or disable the output buffer. The pin name you specify should be the same as the one you use in your RTL design. Setting the output enable signal to high (“1”) in your RTL design enables the output buffer.

  • Page 54: Create A Tx Serializer Interface

    Titanium Interfaces User Guide Create a TX Serializer Interface The following figure shows a completed TX serializer interface, the serialization width is always 4 and m is the number of TX lanes. Figure 20: Complete TX Serializer Interface Block Diagram...

  • Page 55: Create A Rx Deserializer Interface

    Titanium Interfaces User Guide Option Description Mode output Register Option register Enable Serialization Turn on Clock Pin Name Use the slow clock output name that corresponds to the PLL you chose. Serial Clock Use the fast clock output name that corresponds to the PLL you Pin Name chose.

  • Page 56: Design Check: Gpio Messages

    Titanium Interfaces User Guide Option Description The fast clock (INFASTCLK) should be 4 times faster than the slow clock (INCLK). . The serial clock phase shift should be between 45 and 135 degrees. 2. Add a GPIO block with these settings to provide the reference clock input to the PLL:...
  • Page 57 Titanium Interfaces User Guide gpio_rule_input_mode (error) Message For input mode, input must be configured To fix You need to configure the input parameters. Message For input mode, input pin name must be configured To fix Specify a name for the input pin.
  • Page 58 Titanium Interfaces User Guide gpio_rule_inout_mode (error) Message For inout mode, both output and output enable must be configured To fix When using a GPIO block in inout mode, you need to set the options for the output and output enable (as well as the input).
  • Page 59 Titanium Interfaces User Guide gpio_rule_input_alt_conn (error) Message Connection type <type> is not supported by <resource> To fix If you want to use the alternate funciton of a GPIO block, you need to choose a resource that supports it. For example, global control (GCTRL) is only supported on the P pin. You can filter for resources by alternate function in the Resource Assigner.
  • Page 60 Titanium Interfaces User Guide gpio_rule_ddio_pin_name (error) Message Double Data I/O must have both HI and LO input pin names defined To fix When using DDIO, you need to specify pin names for the Pin Name (HI) and Pin Name (LO).
  • Page 61 Titanium Interfaces User Guide gpio_rule_resource (error) Message Resource name is empty Resource is not a valid GPIO device instance To fix You need to choose a valid resource. gpio_rule_io_standard_bank (warning) Message Mismatch voltage in I/O standard assignment in bank (<voltage>) and instance (<io_std>)
  • Page 62 Titanium Interfaces User Guide gpio_rule_serial_output_clk (error) Message Output clock inversion is not allowed with serialization enabled To fix If you use serialization, you cannot also invert the clock. Turn off the Inverted option. gpio_rule_static_input_delay (error) Message Static delay, <int> is outside of limit (0-15) for non-Differential HSTL/SSTL I/O Standard Static delay, <int>...
  • Page 63 Titanium Interfaces User Guide gpio_rule_io_standard_stl (warning) Message Skip checking Vref requirement on a single-ended input configuration: input path is not used To fix You get this warning when the GPIO is in inout mode but you have not specified an input pin name.
  • Page 64 Titanium Interfaces User Guide gpio_rule_serialization (error) Message Register Option has to be set to register when using serialization To fix You cannot use serialization unless the Register Option is set to register. Either change the option or do not use serialization.
  • Page 65 Titanium Interfaces User Guide gpio_rule_deserialization (error) Message Register Option has to be enabled when using deserialization To fix You cannot use deserialization unless the Register Option is set to register. Either change the option or do not use deserialization. Message...
  • Page 66 (error) Message Resource <name> does not support Slew Rate feature. It will be ignored To fix The Titanium HVIO pins do not support slew rate. Either diable that option or choose another resource. gpio_rule_cfg_dyn_delay (error) Message Resource <name> does not support Dynamic Delay feature.

  • Page 67: Chapter 6: Lvds Interface

    Titanium Interfaces User Guide Chapter 6 LVDS Interface Contents: HSIO Configured as LVDS • • Using the LVDS Block • Create an LVDS TX Interface • Create an LVDS RX Interface Design Check: LVDS Errors and Warnings • Each HSIO block can use a pair of I/O pins as an LVDS receiver (RX), transmitter (TX), or bidirectional (RX/TX) signal.
  • Page 68 Titanium Interfaces User Guide Table 37: Full and Half Rate Serialization Mode Description Example Full rate clock In full rate mode, the fast clock runs at Data rate: 800 Mbps the same frequency as the data and Serialization/Deserialization factor: 8...
  • Page 69 Titanium Interfaces User Guide Table 38: LVDS RX Signals (Interface to FPGA Fabric) Signal Direction Clock Domain Description IN[9:0] Output SLOWCLK Parallel input data to the core. The width is programmable. Output Alternate input, only available for an LVDS RX resource in bypass mode (deserialization width is 1;...
  • Page 70 Titanium Interfaces User Guide LVDS TX You can configure an HSIO block as one LVDS TX signal. LVDS TX can be used in the serial data output mode or reference clock output mode. Figure 24: LVDS TX Interface Block Diagram...
  • Page 71 Titanium Interfaces User Guide LVDS Bidirectional You can configure an HSIO block as one LVDS bidirectional signal. You must use the same serialization for the RX and TX. Figure 26: LVDS Bidirectional Interface Block Diagram HSIO Buffer Deserializer LVDS RX...
  • Page 72 Titanium Interfaces User Guide Signal Direction Clock Description Domain DLY_ENA Input SLOWCLK (Optional) Enable the dynamic delay control or the DPA circuit, depending on which one is enabled. DLY_INC Input SLOWCLK (Optional) Dynamic delay control. Cannot be used with DPA enabled. When DLY_ENA is 1,...

  • Page 73: Using The Lvds Block

    Titanium Interfaces User Guide Using the LVDS Block The LVDS block defines the functionality of the LVDS pins. You can choose whether the block is a transmitter (TX), receiver (RX), or bidirectional. LVDS TX Table 42: LVDS TX Options Option...
  • Page 74 Titanium Interfaces User Guide The serial clock (also known as the fast clock) outputs data to the pin, the parallel clock (also known as the slow clock) transfers it from the core. An equation defines the relationship between the clocks. For LVDS TX the parallel clock captures data from the core and the serial clock outputs it to the LVDS buffer.

  • Page 75: Create An Lvds Tx Interface

    Important: You must use the same value for the serialization/deserialization. PLL Requirements for Serial and Parallel Clocks With Titanium FPGAs, you need to use the output clocks from specific PLLs as the LVDS serial and parallel clocks. Table 44: PLL Requirements...
  • Page 76 Titanium Interfaces User Guide 1. Add a PLL block with the following settings: Option Description Resource You can use any PLL resource. T13/T20 BGA169 and BGA256 only: if you also want to create an RX interface, do not select PLL_BR0 because it is the only PLL the RX interface can use.

  • Page 77: Create An Lvds Rx Interface

    Titanium Interfaces User Guide Option Description Output pin/ bus name Parallel clock 1: The output clock from the LVDS TX lane is parallel clock division frequency. 2: The output clock from the TX lane is half of the parallel clock frequency.

  • Page 78: Design Check: Lvds Errors And Warnings

    Titanium Interfaces User Guide 2. Add a PLL block with the following settings: Option Description Resource T13/T20 BGA169 and BGA256 only: Select BR_PLL0, which is the only PLL the LVDS RX interface can use. Reference External Clock Mode Reference Clock...
  • Page 79 Titanium Interfaces User Guide lvds_rule_clkout_mode (error) Message Serial clock name must be configured in clock output mode To fix When you are using the LVDS serializer (serialization width greater than 1), you need to specify the serial clock pin name.
  • Page 80 Titanium Interfaces User Guide lvds_rule_usage (error) Message Resource <res name> was assigned multiple times To fix You cannot assign the same resource to more than one block type. Change the resource to a different one. lvds_rule_rx_alt_conn (error) Message Connection type <type> is not supported by the resource...
  • Page 81 Titanium Interfaces User Guide lvds_rule_rx_clock (error) Message Serial and parallel clocks cannot be the same clock To fix You cannot use the same clock for both the serial (FASTCLK) and parallel (SLOWCLK) clocks. Message Serial clock name is not a PLL output clock To fix Use a PLL output clock as the serial (FASTCLK) clock.
  • Page 82 Titanium Interfaces User Guide lvds_rule_rx_distance (error) Message These HSIO GPIO must be placed at least 1 pair away from LVDS <name> in order to avoid noise coupling from GPIO to LVDS: <violated list> To fix When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO used as LVDS RX in the same bank.
  • Page 83 Titanium Interfaces User Guide lvds_rule_rx_pll_refclk (error) Message Serial clock name is not a PLL output clock To fix Use a PLL output clock as the serial (FASTCLK) clock. Message Parallel clock name is not a PLL output clock To fix Use a PLL output as the parallel (SLOWCLK) clock.
  • Page 84 Titanium Interfaces User Guide lvds_rule_tx_clock (error) Message Serial and parallel clocks cannot be the same clock To fix You cannot use the same clock for both the serial (FASTCLK) and parallel (SLOWCLK) clocks. Message Serial clock name is not a PLL output clock To fix Use a PLL output clock as the serial (FASTCLK) clock.
  • Page 85 Titanium Interfaces User Guide lvds_rule_tx_serial_width (error) Message Unsupported serializaion width: 9 To fix The LVDS block does not support a serialization wiudth of 9. Choose another width. lvds_rule_tx_vref (error) Message This resource is reserved as vref for bank <name>. Us a different resource to configure LVDS...

  • Page 86: Chapter 7: Hyperram Interface

    Ti60 can communicate with the on-board HyperRAM. About the HyperRAM The Titanium FPGA in F100S3F2 package includes a HyperRAM. The HyperRAM has a density of 256 Mbits and a clock rate of up to 250 MHz. The HyperRAM supports double- data rates of up to 500 Mbps and supports a 16 bit data bus.

  • Page 87: Using The Hyperram Interface

    Titanium Interfaces User Guide Signal Direction Description RWDS_OUT_HI [1:0] Input Read/write data strobe input ports for data mask during write operation. Registered in normal mode/resync mode RWDS_OUT_LO [1:0] Input of DDIO. RWDS_OE [1:0] Input Read/write data strobe output enable port.
  • Page 88 Titanium Interfaces User Guide Option Values Notes Active-Low HyperRAM Reset Pin Name User defined Active-Low HyperRAM Chip Select Pin Name User defined Differential Clock Pin Name (P HI) User defined Differential Clock Pin Name (P LO) User defined Differential Clock Pin Name (N HI)

  • Page 89: Chapter 8: Jtag User Tap Interface

    Using the JTAG User TAP Block • Design Check: JTAG User Tap Errors and Warnings Titanium FPGAs have dedicated JTAG pins to support configuration and boundary scan testing. JTAG Mode The JTAG serial configuration mode is popular for prototyping and board testing. The four- pin JTAG boundary-scan interface is commonly available on board testers and debugging hardware.
  • Page 90 Titanium Interfaces User Guide Instruction Binary Description Code [4:0] USERCODE 01101 Use this instruction to program a 32-bit signature into the FPGA during programming. Learn more: Refer to the AN 038: Programming with an MCU and the JTAG Interface for more information about programming Efinix FPGAs with a microcontroller using JTAG mode.
  • Page 91 Titanium Interfaces User Guide Connect the FPGA pins as shown in the following diagrams. Figure 31: JTAG Programming (Packages without MIPI D-PHY Block) Resistors in Configuration Circuitry for the resistor values. VCCIO VCCIO VCCIO VCCIO VCCIO JTAG Cable/Module VCCIO FPGA...

  • Page 92: Using The Jtag User Tap Block

    Add the JTAG User TAP block to your interface if you want to use the FPGA JTAG pins to communicate with the design running in the core. You specify the instruction to use with the JTAG Resource setting. Titanium FPGAs have four JTAG User TAP blocks. To use more than one, add JTAG User TAP blocks to your interface design, one for each resource.

  • Page 93: Design Check: Jtag User Tap Errors And Warnings

    Titanium Interfaces User Guide Signal Direction Description <instance>_CAPTURE Input Capture pin. <instance>_SHIFT Input Shift pin. <instance>_UPDATE Input Update pin. <instance>_TDO Output JTAG test data out pin. Design Check: JTAG User Tap Errors and Warnings When you check your design, the Interface Designer applies design rules to your JTAG User Tap settings.

  • Page 94: Chapter 9: Mipi Rx/Tx Lane Interface

    Titanium Interfaces User Guide Chapter 9 MIPI RX/TX Lane Interface Contents: HSIO Configured as MIPI Lane • • MIPI Groups by Package • Using the MIPI TX Lane or MIPI RX Lane Block • Create a MIPI TX Interface Create a MIPI RX Interface •...
  • Page 95 Titanium Interfaces User Guide MIPI RX Lane In RX mode, the HS (fast) clock comes in on the MIPI clock lane and is divided down to generate the slow clock. The fast and slow clocks are then passed to neighboring HSIO blocks to be used for the MIPI data lanes.
  • Page 96 Titanium Interfaces User Guide Table 50: MIPI RX Lane Signals Interface to MIPI soft CSI/DSI controller with D-PHY in FPGA Fabric Signal Direction Clock Domain Description HS_IN[7:0] Output SLOWCLK High-speed parallel data input. LP_P_IN Output – Low-power input data from the P pad.
  • Page 97 Titanium Interfaces User Guide The clock lane generates the fast clock and slow clock for the RX data lanes within the interface group. It also generates a clock that feeds the global network. The following figure shows the clock connections between the clock and data lanes.
  • Page 98 Titanium Interfaces User Guide MIPI TX Lane In TX mode, a PLL generates the parallel and serial clocks and passes them to the clock and data lanes. Figure 37: MIPI TX Lane Block Diagram LP_P_OE HSIO Buffer LP_P_OUT LP_P_IN VREF...

  • Page 99: Mipi Groups By Package

    Titanium Interfaces User Guide MIPI Lane Pads Table 52: MIPI Lane Pads Signal Direction Description Output Differential pad P. Output Differential pad N. MIPI Groups by Package You can use multiple HSIO as MIPI D-PHY lanes to build complete MIPI interfaces with one clock lane and up to 8 data lanes.
  • Page 100 Titanium Interfaces User Guide Figure 39: 100-Ball FBGA MIPI RX Groups VCCA_TL REF_RES_1B GPIOT_P_01 VCCIO2A_2B VCCA_TR GPIOR_P_19 GPIOR_N_19 PLLIN0 GPIOL_P_13 GPIOL_N_18 GPIOL_P_18 GPIOL_P_17 REF_RES_2A VCCAUX REF_RES_3A GPIOR_N_13 GPIOR_P_14 GPIOR_N_14 CBSEL0 PLLIN0 EXTFB GPIOL_N_13 GPIOL_N_12 GPIOL_P_12 GPIOL_N_17 GPIOL_P_15 GPIOR_N_10 GPIOR_P_13 VCCIO3A...
  • Page 101 Titanium Interfaces User Guide Figure 40: 225-Ball FBGA MIPI RX Groups GPIOL_N_18 GPIOL_03 GPIOL_09 GPIOT_P_03 GPIOT_N_03 GPIOT_N_06 GPIOT_N_07 GPIOT_N_11 GPIOT_P_14 GPIOT_P_17 GPIOR_13 GPIOR_12 GPIOR_19 CLK4_N PLLIN1 GPIOL_P_17 GPIOL_P_18 GPIOL_04 VCCIO33_TL GPIOL_10 GPIOT_P_01 GPIOT_P_06 GPIOT_P_07 GPIOT_P_11 GPIOT_N_14 GPIOT_N_17 GPIOR_15 VCCIO33_TR GPIOR_18...
  • Page 102 Titanium Interfaces User Guide Figure 41: 484-Ball FBGA MIPI RX Groups GPIOB_N_12 GPIOB_N_16 GPIOB_P_16 GPIOB_N_21 GPIOB_P_21 GPIOB_N_25 GPIOB_P_25 GPIOB_N_28 GPIOB_P_28 GPIOB_P_32 GPIOB_N_32 GPIOR_N_16 GPIOR_P_16 GPIOR_P_23 GPIOR_N_23 GPIOR_P_26 GPIOR_P_31 GPIOR_N_31 GPIOR_N_42 GPIOR_P_42 _SSU_N _CLK3_N _EXTSPICLK _CDI8 _CDI9 _CDI14 _CDI15 _CDI20 _CDI21...

  • Page 103: Using The Mipi Tx Lane Or Mipi Rx Lane Block

    Titanium Interfaces User Guide Using the MIPI TX Lane or MIPI RX Lane Block The following tables show how to implement a MIPI TX Lane or MIPI RX Lane block. Later sections explain how to build a complete interface. MIPI TX Lane Block...

  • Page 104: Create A Mipi Tx Interface

    Titanium Interfaces User Guide Create a MIPI TX Interface To build a complete MIPI TX interface you need to have at least one data lane and one clock lane. Unlike MIPI RX, they can be in any MIPI group. The following figure shows the blocks used for a complete MIPI TX interface.
  • Page 105 Titanium Interfaces User Guide Option Description FASTCLK_D—Frequency is the speed you are running the PHY, phase shift 45.00° FASTCLK_C—Frequency is the speed you are running the PHY, phase shift 135.00° For example, if the PHY is running at 1,000 Mbps, FASTCLK_D and FASTCLK_C will run at half that 500 MHz (because it transfers data on both clock edges), and SLOWCLK will run at 125 MHz.

  • Page 106: Create A Mipi Rx Interface

    Titanium Interfaces User Guide Create a MIPI RX Interface To build a complete MIPI RX interface you need to have at least one data lane and one clock lane in the same MIPI group. The following figure shows the blocks used for a complete MIPI RX interface.

  • Page 107: Design Check: Mipi Lane Messages

    Titanium Interfaces User Guide Design Check: MIPI Lane Messages When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.
  • Page 108 Titanium Interfaces User Guide mipi_ln_rule_tx_clock (error) Message Serial and parallel clocks cannot be the same clock To fix You cannot use the same clock for both the serial (FASTCLK_C or FASTCLK_D) and parallel (SLOWCLK) clocks. Message Serial clock name is not a PLL output clock To fix Use a PLL output clock as the serial (FASTCLK_C or FASTCLK_D) clock.
  • Page 109 Titanium Interfaces User Guide mipi_ln_rule_tx_param (error) Message Invalid parameters configuration: <features> To fix One of the parameters you set was incorrect. Review any other errors for details. mipi_ln_rule_usage (error) Message Resource <res name> was assigned multiple times To fix You get this error if you choose the same resource for more than one block type (LVDS, MIPI DPHY, or GPIO).

  • Page 110: Chapter 10: Mipi D-Phy Interface

    Important: All information is preliminary and pending definition. In addition to the HSIO, which you can configure as MIPI RX or TX lanes, Titanium FPGAs have hardened MIPI D-PHY blocks, each with 4 data lanes and 1 clock lane. The MIPI D-PHY RX and MIPI D-PHY TX can operate independently with dedicated I/O banks.
  • Page 111 Titanium Interfaces User Guide Figure 44: MIPI RX D-PHY x4 Block Diagram HS_CLK_ACTIVE RXDP/N4 HS_LANn_ACTIVE RXDP/N3 HS_LANn_VALID RXDP/N2 Pads HS_LANn_SYNC RXDP/N1 High-Speed HS_LANn_SKEWCAL RXDP/N0 Mode Signals HS_LANn_DATA [15:0] HS_LANn_SOT_ERR CAL_CLK HS_LANn_SOTSYNC_ERROR BYTE_CLKOUT LP_CLK Clocks LPDT_RX_ENTER ESC_LANn_CLKOUT LPDT_RX_DATA [7:0] ESC_CLK LPDT_RX_VALID...
  • Page 112 Titanium Interfaces User Guide Table 56: MIPI RX D-PHY Control and Status Signals (Interface to FPGA Fabric) Signal Direction Clock Domain Notes RESET Input Reset. Disables PHY and reset the digital logic. RST0_N Input BYTE_CLKOUT Asynchronous FIFO reset and synchronous out of reset.

  • Page 113: Mipi Tx D-Phy

    Titanium Interfaces User Guide Signal Direction Clock Domain Notes LDPT_TX_VALID Input ESC_CLK Lane 0 LPDT TX Data Valid. LPDT_TX_READY Output ESC_CLK Lane 0 LDPT TX Data Ready. Table 59: MIPI RX D-PHY ULP Sleep Mode Signals (Interface to FPGA Fabric)
  • Page 114 The MIPI TX D-PHY block requires an escape clock (ESC_CLK) for use when the MIPI interface is in escape (low-power) mode, which runs up to 20 MHz. Note: Efinix recommends that you set the escape clock frequency as close to 20 MHz as possible. Figure 47: MIPI TX D-PHY Interface Block Diagram...
  • Page 115 Titanium Interfaces User Guide Table 61: MIPI TX D-PHY Clocks Signals (Interface to FPGA Fabric) Signal Direction Clock Domain Notes REF_CLK Input Reference Clock. The clock must be between 12 MHz to 52 MHz. ESC_CLK Input Escape Mode Transmit Clock, used to generate escape sequence.
  • Page 116 Titanium Interfaces User Guide Signal Direction Clock Domain Notes HS_LANn_SKEWCAL Input BYTE_CLKOUT HS Skew Calibration (Lane N). HS_LANn_HIGHVALID Input BYTE_CLKOUT HS High Byte Valid (Lane N) for 16-bit mode. HS_LANn_DATA [15:0] Input BYTE_CLKOUT HS Transmit Data (Lane N). HS_LANn_READY Output BYTE_CLKOUT HS Transmit Ready (Lane N).

  • Page 117: Mipi Dphy Tx Interface Designer Settings

    Titanium Interfaces User Guide MIPI DPHY TX Interface Designer Settings The following tables describe the settings for the Titanium MIPI DPHY TX blocks in the Interface Designer. Table 68: Base Tab Parameter Choices Notes PHY bandwidth in Integer up to 2500 Specify the bandwidth.
  • Page 118 Choose the number of lanes. Default: 4 Width of the data bus 8, 16 Specify the width. Default: 8 <description> Pin Name User defined Data lane pin names. Efinix recommends that you use the defaults. Table 72: Lane Mapping Tab Parameter Choices Notes Phy Lane n clk, data0.

  • Page 119: Mipi Dphy Rx Interface Designer Settings

    Titanium Interfaces User Guide MIPI DPHY RX Interface Designer Settings The following tables describe the settings for the Titanium MIPI DPHY RX blocks in the Interface Designer. Table 74: Base Tab Parameter Choices Notes Instance Name User defined MIPI RX Resource None, MIPI_RX0, Choose the resource.
  • Page 120 Titanium Interfaces User Guide Table 78: Lane Mapping Tab Parameter Choices Notes Phy Lane n clk, data0, data1, The MIPI TX block supports 4 data lanes and 1 clock data2, data3, unused lane. Choose which lane to associate with the MIPI pad.

  • Page 121: Chapter  11:  Pll

    Design Check: PLL Errors About the PLL Interface Titanium FPGAs have PLLs to synthesize clock frequencies. The PLLs are located in the corners of the FPGA. You can use the PLL to compensate for clock skew/delay via external or internal feedback to meet timing requirements in advanced application. The PLL reference clock has up to four sources.
  • Page 122 Titanium Interfaces User Guide Local and Core Feedback Mode Where: is the voltage control oscillator frequency is the post-divider PLL VCO frequency = (F x M x O x C is the output clock frequency is the reference clock frequency...

  • Page 123: Using The Pll V3 Block

    Using the PLL V3 Block Titanium FPGAs have a PLL block that lets you configure the reference clock, feedback options, frequency, and output clocks for the PLL. This PLL is referenced as V3. You set up the PLL using the PLL Clock Calculator, which provides an easy-to-use graphical way to specify the frequencies and other settings.

  • Page 124: Understanding Pll Phase Shifting

    Titanium Interfaces User Guide The Titanium PLL supports dynamic phase shifting. To enable it, click the Dynamic button for the clock output. The calculator adds three additional pins that you use to control the dynamic shifting. You need to specify the pin names.

  • Page 125: Implementing A Zero-Delay Buffer

    VCO frequency Implementing a Zero-Delay Buffer Titanium PLLs can implement a zero-delay buffer circuit. In this mode, the PLL removes all of the clock-insertion delay from the input I/O buffer and core clock tree. You may want to use this buffer when you have a single clock signal that fans out to more than one destination...

  • Page 126: Design Check: Pll Errors

    The following code example shows an .isf that implements a zero-delay buffer for the Ti60 F225. # Efinity Interface Configuration # Version: 2021.1.165.2.19 # Date: 2021-09-23 15:23 # Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved. # Device: Ti60F225 # Package: 225-ball FBGA (preliminary) # Project: r4000 # Configuration mode: active (x1)
  • Page 127 Titanium Interfaces User Guide pll_rule_dynamic_shift_pin (error) Message Dynamic phase shift is enabled but missing pin names: <list> To fix For a PLL output, if you are turn on Dynamic for the phase shift, you also need to specify names for the SHIFT, SHIFT_SELECT, and SHIFT_ENA pins.
  • Page 128 Titanium Interfaces User Guide pll_rule_input_freq (error) Message Input Frequency <float> MHz (after pre-divider) is out of range. Min=<float>MHz Max=<float>MHz To fix Assign the reference clock frequency to a value within the specified range. pll_rule_input_freq_limit (error) Message Input Frequency <float> MHz is out of range. Min=<float>MHz Max=<float>MHz To fix Assign the right reference clock frequency.
  • Page 129 Titanium Interfaces User Guide pll_rule_output_name (error) Message PLL output clock names have to be unique. Duplicates found: <list of string> To fix You get this error when you use duplicate clock names. Rename them. pll_rule_output_number (error) Message Output number for <clk name> is invalid. It must be between 0 to <int>...
  • Page 130 Titanium Interfaces User Guide pll_rule_refclk (error) Message Bonded external reference clock pin has to be specified in dynamic mode To fix When using dynamic as the Clock Source, the PLL expects to find the resource for the external clock(s). Add a GPIO block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under Dynamic Clock.

  • Page 131: Chapter 12: Oscillator

    3. Choose the clock frequency (10, 20, 40, or 80). 4. Specify the instance name and clock pin. Note: You can disable the internal oscillator in Titanium FPGAs. The internal oscillator is disabled if it is not instantiated in the Efinity Interface Designer.
  • Page 132 Specify a valid instance name. osc_rule_resource (error) Message Resource name is empty Resource is not a valid oscillator device instance To fix Although Titanium FPGAs only have one oscillator, you still need to choose the resource when you create an oscillator block. www.efinixinc.com...

  • Page 133: Chapter 13: Spi Flash Interface

    • Using the SPI Flash Interface Titanium Ti35 and Ti60 FPGAs in the F100 package have an integrated SPI flash memory. About the SPI Flash Memory Titanium FPGAs in the F100S3F2 package include a SPI flash memory. The SPI flash memory has a density of 16 Mbits and a clock rate of up to 85 MHz.

  • Page 134: Using The Spi Flash Interface

    Titanium Interfaces User Guide Using the SPI Flash Interface The on-board flash is 16 Mbits and can hold: • 1 uncompressed bitstream or • 2 compressed bitstreams (typical designs) or • 1 compressed bitstream and user data Note: The maximum bitstream size for Ti35 and Ti60 FPGAs is about 13.7 Mbits; compression typically reduces the size by about 50%.

  • Page 135: Chapter 14: Interface Floorplans

    Titanium Interfaces User Guide Chapter 14 Interface Floorplans Note: The numbers in the floorplan figures indicate the HVIO and HSIO number ranges. Some packages may not have all HVIO or HSIO pins in the range bonded out. Floorplan Diagram for FPGAs in W64 Packages...
  • Page 136 Titanium Interfaces User Guide Floorplan Diagram for FPGAs in F225 Packages Figure 55: Ti35 and Ti60 FPGAs Left Right PLL_TL PLL_TR Quantum Compute Fabric I/O bank HVIO Dedicated blocks HSIO Dimensions not to scale PLL_BL PLL_BR Floorplan Diagram for FPGAs in F484 Packages...

  • Page 137: Icon Reference

    Titanium Interfaces User Guide Icon Reference Interface Designer Icons Export GPIO Assignments Interface Designer Resource Assigner Toggle Instance View and Resource View Import GPIO Assignments Add Block Clear Resource Check Design for Errors Create a GPIO bus Clear All Resources...

  • Page 138: Revision History

    Version Description February 2022 Added Titanium DDR block interface description. Added Titanium MIPI DPHY interface block description. HVIO I/O banks support dynamic voltage shifting. (DOC-444) Added MIPI RX clock groups for F484 package. Added interface floorplan for F484 package. New design rules: io_bank_rule_mode_sel, io_bank_rule_dyn_voltage.

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