User Manuals: Efinix Titanium FPGA Development Kit

Manuals and User Guides for Efinix Titanium FPGA Development Kit. We have 1 Efinix Titanium FPGA Development Kit manual available for free PDF download: User Manual

Efinix Titanium User Manual

Efinix Titanium User Manual (138 pages)

Brand: Efinix | Category: Microcontrollers | Size: 2 MB

Table of Contents

Table of Contents
2
About the Interface Designer
4
Chapter 1: Get Oriented

5
Chapter 2: Device Settings

17
- Configuration Interface
  17
- Enable Internal Configuration
  17
- About SEU Detection
  17
- Enable SEU Detection
  18
- SEU Detection Circuitry
  19
- Design Check: Configuration Messages
  20
- I/O Banks Interface
  21
- Titanium I/O Banks
  21
- Dynamic Voltage Support
  22
- Design Check: I/O Bank Messages
  23
Chapter 3: Clock and Control Networks

24
Chapter 4: DDR Interface

31
- About the DDR DRAM Interface
  31
- DDR Interface Designer Settings
  37
Chapter 5: GPIO Interface

39
- Types of GPIO
  39
- Features for HVIO and HSIO Configured as GPIO
  41
- Double-Data I/O
  42
- Programmable Delay Chains
  43
- About the HVIO Interface
  44
- About the HSIO Interface
  46
- HSIO Configured as GPIO
  47
- Using the GPIO Block
  50
- Using the GPIO Bus Block
  53
- Create a TX Serializer Interface
  54
- Create a RX Deserializer Interface
  55
- Design Check: GPIO Messages
  56
Chapter 6: LVDS Interface

67
Chapter 7: Hyperram Interface

86
- About the Hyperram
  86
- Using the Hyperram Interface
  87
Chapter 8: JTAG User TAP Interface

89
Chapter 9: MIPI RX/TX Lane Interface

94
- HSIO Configured as MIPI Lane
  94
- MIPI Groups by Package
  99
- Using the MIPI TX Lane or MIPI RX Lane Block
  103
- Create a MIPI TX Interface
  104
- Create a MIPI RX Interface
  106
- Design Check: MIPI Lane Messages
  107
Chapter 10: MIPI D-PHY Interface

110
- Mipi Rx D-Phy
  110
- Mipi Tx D-Phy
  113
- MIPI DPHY TX Interface Designer Settings
  117
- MIPI DPHY RX Interface Designer Settings
  119
Chapter 11: PLL

121
- About the PLL Interface
  121
- Using the PLL V3 Block
  123
- Using the PLL Clock Calculator
  123
- Understanding PLL Phase Shifting
  124
- Manually Configuring the PLL
  124
- Implementing a Zero-Delay Buffer
  125
- Design Check: PLL Errors
  126
Chapter 12: Oscillator

131
- Using the Oscillator Block
  131
- Design Check: Oscillator Errors
  131
Chapter 13: SPI Flash Interface

133
- About the SPI Flash Memory
  133
- Using the SPI Flash Interface
  134
Chapter 14: Interface Floorplans

135
- Icon Reference
  137
- Revision History
  138

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