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4. SYSTEM CONFIGURATION
1
Theory of Operat ion
The block diagram of t h i s component i s shown below.
The d i g i t a l s i g n a l
interface 1C v i a the bus transceiver.
in the timing complying with IEEE488-1978.
The received code i s then decoded by the CPU. The CPU converts the data into
the binary type.
Data i s sent from the s e r i a l output port to the D/A.
data passes through the photo i s o l a t o r and i s insulated.
Data i s converted into p a r a l l e l data by the s h i f t r e g i s t e r and fed to the D/A
converter.
The analog output of the D/A c o n v e r t e r passes through the re lay
and i s output.
This relay performs switching over remote and l o c a l .
In addition, the CPU controls the control connector and processes SRQ.
Block diagram
CONT A
CONT B
input
from the GP-IB c o n n e c t o r
This GP-IB interface performs handshaking
GP-IB connector
GP-IB bus transceiver
GP-IB interface IC
CPU
ROM
RAM
F o r t
Photo isolator
fa Sell
r e 8 i s l c r
D/A
Realy
OUT A
- 7 -
i s f e d to t h e GP-IB
Photo isolator
Photo isolator
S h i f t register
f a l c i i
r e 8
*
s l e r
latch
D/A
Realy
OUT B
Then,
D/A
Realy
OUT C
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