Gigabyte H262-P61 User Manual page 61

Parameter
AtomicOp Egress Blocking
IDO Request Enable
IDO Completion Enable
LTR Mechanism Enable
End-End TLP Prefix Blocking
PCI Express GEN2 Link Register
Settings
Compliance SOS
Hardware Autonomous Width
Hardware Autonomous Speed
Description
If supported by hardware and set to 'Enabled', outbound
AtomicOp Requestsvia Egress Ports will be blocked.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Enabled', this permits setting
the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests
to be initiated.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Enabled', this permits setting
the number of ID-Based Ordering (IDO) bit (Attribute[2]) requests
to be initiated.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Enabled', this enables the
Latency Tolerance Reporting (LTR) Mechanism.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Enabled', this function will
block forwarding of TLPs containing End-End TLP Prefixes.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Enabled', this will force
LTSSM to send SKP Ordered Sets between sequences when
sending Compliance Pattern or Modified Compliance Pattern.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Disabled', this will disable
the hardware's ability to change link width except width size
reduction for the purpose of correcting unstable link operation.
Options available: Enabled, Disabled. Default setting is Disabled.
If supported by hardware and set to 'Disabled', this will disable
the hardware's ability to change link speed except speed rate
reduction for the purpose of correcting unstable link operation.
Options available: Enabled, Disabled. Default setting is Disabled.
BIOS Setup
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