Sanyo CE28CH3-C Service Manual page 7

CHASSIS DESCRIPTION
C
C
B'
B
B
A'
A
A
50Hz
100Hz
A' = A, B'= B
(b) Double Scan
(a) Normal Scan
Fig.-7
The U/V-signals are converted in progressive at multiplexer and converted from A to D in 8 bit,
and then applied from pins 34 to 41 of IC7201 to pins 1 to 40 and 24 to 27 of IC7203
<MSM518221A>, video memory, for writing.
The signals are wrote down to memory IC by 16MHz clock. It means the number of sampling are
1024 per 1H. The clock signal for writing is obtained by performing the phase comparing AFC
control to the HD-signal. The phase comparing AFC control performs at IC7205<TLC2932I>, PLL,
and IC7201. The 32MHz clock signal generated here is supplied from pin 3 of IC7205 and sent to
pin 61 of IC7201. The clock signal divided to 16MHz in the IC is output to pin 31 and supplied to
pins 6 of IC7202 and IC7203.
The reading is performed by 32MHz clock supplied from pin 28 of IC7201. In this case, the
number of sampling is 2048 per 1H. This read clock signal is obtained by performing the
frequency comparing AFC control to the input HD-signal. To avoid the skew distortion, the phase
comparing AFC control is not employed. The frequency comparing AFC control is performed at
IC7204<TLC2932I>, PLL, and IC7201. The 32MHz clock signal generated here is output from pin
3 of IC7205 and sent to pins 56 of IC7201 and IC7203.
The Y/U/V-signals are converted in progressive as the writing for 16MHz and reading for 32MHz.
The progressive V-signal output from pins 10 to 13 and 15 to 18 of IC7202 is supplied to pins 9 to
16. Also, the progressive U/V-signals output from pins 10 to 13 and 15 to 18 of IC7203 are
supplied to pins 43 to 50 of IC7201 and separated with U-signal and V-signal. And then, Y/U/V-
signals are converted in D to A in IC7201 and output to pin 6 as analogue Y-signal, pin 98 as
analogue V-signal and pin 100 as analogue V-signal respectively. The HD-signal progressive
converted in IC7201 is output from pin 71 of IC7201, the VD-signal progressive converted in
IC7202 is output from pin 70 of IC7201. The output HD and VD signals are sent to IC202 with
positive polarity through the IC7341 for waveform shaping.
The Y-signal output from IC7201 is controlled the amplitude level and band-pass limiting at the
circuit consist of Q7351, Q7352, Q7353, Q7354 and 16MHz LPF. The U/V-signals are also
controlled the amplitude level and band-pass limiting at the circuit consist of Q7361, Q7362,
Q7363, Q7364, Q7371, Q7372, Q7373, Q7374 and 8MHz LPF and these signals are sent to
IC201.
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C5WHV