14.2. Main Block Diagram
SU
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
S.R
64
SD
H3
+
SP
-
R
SPEAKER
TERMINAL
TH-50PHD6/TH-50PHW6 MAIN Block Diagram
S.R.
S.R.
C12
C13
SC12
SC13
SC2 SC23
D
SC
SC20
D20
CONTROL
PULSE
INITIALIZE
PULSE
J
SCAN
VOLTAGE
LVDS
TRANSMITTER
SC62
C6
C62
S.R.
S.R.
S.R.
S.R.
C1
HD/VD
SYNC PROCESSOR/
DISCHARGE
CONTROL
CONTROL
MAIN MPU
ROM
SUB MPU
VD
HD
24bit
BUS
LVDS
A/D
LVDS
A/D
D5
D6
J5
J6
ANALOG SW
J11
J12
A/D
SW
C Y V
R L
R L
R G B HDVD
S.R.
S.R.
S.R.
C10
C20
C22
C11
C24
FORMAT
CONVERTER
RGB
PROCESSOR
SDRAM
VD
HD
D3
J3
SYNC
SEPARATOR
SYNC
SW
J14
HX
HY
PC RS-232C
PC AUDIO IN
C54
C5
C61
C52
C60
C50
S.R.
S.R.
S.R.
C2
C25
D31
D32
PLASMA AI
SUB-FIELD
PROCESSOR
SDRAM
ROM
SDRAM
PLASMA AI
SUB-FIELD
PROCESSOR
D34
D33
C55
S.R.
S.R.
58