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4
Internal block diagram
MD2
MD1
MD0
EXTAL
XTAL
Φ
STBY
RES
RES0
NMI
P66/LWR
P65/HWR
P64/RD
P63/AS
P62/BACK
P61/BREQ
P60/WAIT
P84/CS0
P83/CS1/IRQ3
P82/CS2/IRQ2
P81/CS3/IRQ1
P80/RFSH/IRQ0
*ROM capacity
H8/3042
64KByte
H8/3041
48KByte
H8/3040
32KByte
HS/300H CPU
Interruption
controller
ROM*
(Mask ROM)
RAM
16-bit integrated
timer pulse unit
(ITU)
Programmable
timing pattern
controller (TPC)
Port B
Port A
Port 3
Port 4
Address bus
Address bus (Upper)
Address bus (Lower)
DMA
contorller
(DMAC)
Refresh
controller
Watchdog timer
serial communication
interface
(SCI) x 2ch
A/D convertor
D/A convertor
12 – 5
PS3/A19
PS2/A18
PS1/A17
PS0/A16
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RXD1
P92/RXD0
P91/TXD1
P90/TXD0
Port 7
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