Gigabyte GA-7DPXDW User Manual page 37

C SDRAM ECC Setting
8Check only Detects only.
8Correct error Allows the correct i on of singl e -bit errors and the det e ction of multiple-bit errors.
Detects , corrects read errors, and writes the corrected data to memory.
8Correct+scrub
Disabled SDRAM ECC Setting.(Default Value)
8Disabled
C Super Bypass Mode
The chipset internally bypasses certain memory to CPU pipe stages for
8Enabled
optimal performance. (Default Value)
Disabled Super Bypass Mode.
8Disabled
C DDR SDRAM Timing by
The system will automatically set proper values to DDR SDRAM Idle Limit,
8Auto
Page Hit Limit , Trc Cycl e , Trp Cycle, Tras Cycle, CAS Latency Cycle and
Trcd Cycle. (Default Value)
Set DDR SDRAM Timing by Manual.
8Manual
37
BIOS Setup