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Diodes PI7C9X2G304EL Manual

Pci express gen 2 packet switch 3-port, 4-lane, extremelo pcie2.0 packet switch
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PI7C9X2G304EL
PCI EXPRESS GEN 2 PACKET SWITCH
3-Port, 4-Lane, ExtremeLo PCIe2.0 Packet Switch
DATASHEET
REVISION 2-2
September 2017
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-434-1040
Internet:
http://www.diodes.com
Document Number DS39931 Rev 2-2

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Summary of Contents for Diodes PI7C9X2G304EL

  • Page 1 PI7C9X2G304EL PCI EXPRESS GEN 2 PACKET SWITCH 3-Port, 4-Lane, ExtremeLo PCIe2.0 Packet Switch DATASHEET REVISION 2-2 September 2017 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS39931 Rev 2-2...
  • Page 2 Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies w hose products are represented on Diodes Incorporated w ebsite, harmless against all damages.
  • Page 3 Updated Table 12-2 DC Electrical Characteristics Added Section 12.4 Operating Ambient Temperature Added Section 12.5 Power Consumption Revision numbering system changed to whole number PI7C9X2G304EL Page 4 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 4: Table Of Contents

    6.1.4 MAPPIN G EEPROM CONTENTS TO C ONFIGURATION REGISTERS ..........29 INTERFA CE ..............................36 REGISTER DES CRIPTION ................................ 37 REGISTER TYPES ..............................37 PI7C9X2G304EL Page 5 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 5 XPIP_CSR4 – OFFSET 84h ..........................53 7.2.53 XPIP_CSR5 – OFFSET 88h ..........................53 7.2.54 TL_CSR – OFFSET 8Ch........................... 54 7.2.55 PHY PARAMETER 3 – OFFSET 90h ......................55 PI7C9X2G304EL Page 6 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 6 POWER BUDGET C APABILITY REGISTER – OFFSET 218h ............77 7.2.109 ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only)....77 7.2.110 ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only)........77 PI7C9X2G304EL Page 7 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 7 AC SPECIFICATIONS .............................. 86 12.4 OPERATING AM BIENT TEMPERATURE ......................88 12.5 POW ER CONSUMPTION ............................88 13 PACKAGE INFORMATION ............................... 89 14 ORDERING INFORMATION..............................91 PI7C9X2G304EL Page 8 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 8 PI7C9X2G304EL TABLE OF FIGURES 5-1 D ..........................20 IGURE RIVER UTPUT AVEFORM 6-1 SMB PI7C9X2G304EL..............36 IGURE RCHIT ECTURE MPLEMENTATION ON 11-1 I ..........................85 IGURE NIT IAL OWER EQUENCE 13-1 P ..........................89 IGURE ACKAGE OUT LINE DRAWING 13-2 P ............................

  • Page 9: Features

    • Low Power Dissipation: 650 mW typical in L0 normal mode • Industrial Temperature Range -40 to 85 • 136-pin aQFN 10mm x 10mm package PI7C9X2G304EL Page 10 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 10: General Description

    ACS to avoid possible performance bottleneck associated with re-direction, wh ich introduces extra latency and may increase link and RC congestion. PI7C9X2G304EL Page 11 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 11 The clock buffer is fro m a single 100M Hz clock input, and distributes the clock source to three outputs, which can be used by the downstream PCI Exp ress end devices. The clock buffer feature can be enabled and disabled by strapping pin setting. PI7C9X2G304EL Page 12 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 12: Pin Description

    However, if pin is connected to a board trace and not driven, it is recommended that an external 330-ohm pull-down resistor be used. PI7C9X2G304EL Page 13 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 13: Port Configuration Signals

    EEPROM. The pin is set to ‘1’ by default. SMBCLK SM Bus Clock: System management Bus Clock. This pin requires an external 5.1K-ohm pull-up resistor. PI7C9X2G304EL Page 14 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 14 AE35, AJ1, AK2, AL1, AM2, AN1, AP1, AP2, AP4, AP16, AP24, AP26, AP32, AP34, AP35, AR1, AR3, AR17, AR21, AR23, AR25, AR27, AR29, AR33, AR35 PI7C9X2G304EL Page 15 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 15: Jtag Boundary Scan Signals

    V34, AB34 Ground: Used as reference clock ground pins. Ground: Used as analog ground pins. AGND B18, B22 VSS Ground: Used as ground pins. PI7C9X2G304EL Page 16 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 16: Pin Assignments

    SLOT CLK VDDC PERP[2] T EST 3 GPIO[0] VDDC CGND AP10 GPIO[3] PERN[1] VC1_EN AP12 GPIO[6] PERP[1] REFCLKO_N[1] AP14 SLOT _IMP[1] PRSNT [1] AP16 PI7C9X2G304EL Page 17 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 17: Functional Description

    Thre shold 1.0 us 2.0 us 4.0 us (Recommended) 5.0 us 10 us 20 us 40 us 50 us Multiple lanes could share the PLL. PI7C9X2G304EL Page 18 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 18: Receiver Signal Detection

    The final drive amp litude and drive de-emphasis are the summation of the base level value and the offset value. The offset value for drive amplitude is 25 mV pd, and 6.25 mV pd for drive de-emphasis. PI7C9X2G304EL Page 19 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 19: Drive Amplitude

    01011 10010 00101 01100 10011 00110 01101 Others Reserved Note : 1. Nominal levels. Actual levels will vary with temperature, voltage and board effects. PI7C9X2G304EL Page 20 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 20: Drive De-Emphasis

    (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be sent out to acknowledge on reception of a good TLP. PI7C9X2G304EL Page 21 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 21: Transaction Layer Receive Block (Tlp Decapsulation)

    VC0 channel by default. After the TC/ VC mapping, the receive b lock dispatches the incoming request, completion, or data into the appropriate VC0 and VC1 queues. PI7C9X2G304EL Page 22 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 22: Queue

    Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express Switch including Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer PI7C9X2G304EL Page 23 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 23: Port Arbitration

    Virtual Channel 0. PI7C9X2G304EL Page 24 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 24: Vc Arbitration

    Endpoint, validating every Request transaction between two downstream co mponents and enabling direct routing of peer-to-peer Memory Requests whose addresses have been Translated when ATS system is being used. PI7C9X2G304EL Page 25 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 25: Eeprom Interface And System Management Bus

    Global XPIP_CSR5[15:0] for Port 0~2 Buffer_ctrl[4:0] / Global XPIP_CSR5[23:16] for Port 0~2 Globe XPIP_CSR6[7:5] for Port 0~2 MAC_CT R / Global PHY Parameter 3 for Port 0~2 PI7C9X2G304EL Page 26 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 26 XPIP_CSR5[30:24] for Port 1 PM Control Para/Rx Polarity for Port 1 XPIP_CSR5[30:24] for Port 2 PM Control Para/Rx Polarity for Port 2 Reserved Reserved Reserved PI7C9X2G304EL Page 27 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 27 Maximum T ime Slot for Port 0 T C/VC Map for Port 2 (VC1) Maximum T ime Slot for Port 0 Reserved Reserved Reserved Reserved Reserved PI7C9X2G304EL Page 28 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 28: Mapping Eeprom Contents To Configuration Registers

    Bit [14]: LTR capability enable  8Ch (Port 0~2) 4KB Boundary Check Enable for Port 0~2 8Ch: Bit [3] Bit [15]: Enable 4KB Boundary Check  PI7C9X2G304EL Page 29 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 29  78h: Bit [10] Bit [12]: L0s  78h (Port 0) Change_Speed_Sel for Port 0 78h: Bit [13:12] Bit [14:13]: Change Speed select  PI7C9X2G304EL Page 30 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 30 Bit [15:14] : DO_CHG_DATA_CNT_SEL  7Ch (Port 2) PHY Parameter 2_1 for Port 2 7Ch: Bit [12 :8] Bit [4:0]: PHY parameter 2  PI7C9X2G304EL Page 31 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 31 VC0 TC/VC Map for Port 0 154h: Bit [7:1] Bit [15:9]: When set, it indicates the corresponding T C is mapped  into VC0 PI7C9X2G304EL Page 32 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 32 VGA De code Enable for Port 0 70h: Bit [31] Bit [7]: Enable VGA decode  88h (Port 0) XPIP_CSR5[31:24] for Port 0 88h: Bit [31:24] Bit[15:8]: XPIP_CSR5[31:24] PI7C9X2G304EL Page 33 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 33 Bit [30:16]: Acknowledge Latency Timer  70h (Port 2) Acknowledge Latency Timer for Port 2 70h: Bit [30:16] Bit [30:16]: Acknowledge Latency Timer  PI7C9X2G304EL Page 34 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 34 160h (Port 2) TC/VC Map for Port 2 160h: Bit [7:0] Bit [15:8]: When set, it indicates the corresponding T C is mapped  into VC1 PI7C9X2G304EL Page 35 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 35: Smbus Interface

    The PI7C9X2G304EL p rovides the System Management Bus (SM Bus), a two-wire interface through which a simp le device can commun icate with the rest of the system. The SM Bus interface on the PI7C9X2G304EL is a bi-directional slave interface. It can receive data fro m the SM Bus master or send data to the master. The interface allo ws full access to the configuration registers.

  • Page 36: Register Description

    ACK Latency T imer Replay T ime-out Counter PHY Parameter 0 Switch Modes PHY Parameter 1 XPIP_CSR2 PHY Parameter 2 XPIP_CSR3 XPIP_CSR4 XPIP_CSR5 XPIP_CSR7 XPIP_CSR6 T L_CSR PI7C9X2G304EL Page 37 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 37 Port Arbitration T able with 128 Phases for VC0 180h – 1BCh Port Arbitration T able with 128 Phases for VC1 1C0h – 1FCh Reserved 200h – 20Bh PI7C9X2G304EL Page 38 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 38: Vendor Id Register - Offset 00H

    Does not apply to PCI Express. Must be hardwired to 0b. Invalidate Enable VGA Palette Snoop Does not apply to PCI Express. Must be hardwired to 0b. Enable PI7C9X2G304EL Page 39 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 39: Primary Status Register - Offset 04H

    Set to 1 whenever the primary side of the port in a Switch receives a Poisoned T LP. Detected Parity Error Reset to 0b. PI7C9X2G304EL Page 40 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 40: Revision Id Register - Offset 08H

    Indicates the number of the PCI bus to which the secondary interface is Secondary Bus connected. T he value is set in software during configuration. 15:8 Number Reset to 00h. PI7C9X2G304EL Page 41 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 41: Subordinate Bus Number Register - Offset 18H

    Does not apply to PCI Express. Must be hardwired to 0b. Signaled T arget Set to 1 (by a completer) whenever completing a request in the secondary PI7C9X2G304EL Page 42 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 42: Memory Base Address Register - Offset 20H

    T he lower 20 bits are assumed to be 0. T he memory base register upper 32 Base Address [31:20] bits contain the upper half of the base address. Reset to 000h. PI7C9X2G304EL Page 43 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 43: Prefetchable Memory Limit Address Register - Offset 24H

    I/O Limit Address, Bridge to determine when to forward I/O transactions from one interface to 31:16 Upper 16-bits the other. [31:16] Reset to 0000h. PI7C9X2G304EL Page 44 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 44: Capability Pointer Register - Offset 34H

    1b: Executes 16-bit address decoding on VGA I/O accesses VGA 16-bit decode Reset to 0b. Master Abort Mode Does not apply to PCI Express. Must be hardwired to 0b. PI7C9X2G304EL Page 45 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 45: Power Management Capability Register - Offset 40H

    11b: D3 hot state Reset to 00b. Reserved RsvdP Not Support. No_Soft_Reset When set, this bit indicates that device transitioning from D3hot to D0 does PI7C9X2G304EL Page 46 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 46: Ppb Support Extensions - Offset 44H

    INT x # pin Reset to 0b. Multiple Message Read as 000b. 19:17 Capable Multiple Message Reset to 000b. 22:20 Enable PI7C9X2G304EL Page 47 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 47: Message Address Register - Offset 50H (Downstream Port Only)

    Contains DWORD address that is used to generate read or write cycle to the VPD table stored in EEPROM. 23:18 VPD Address Reset to 00_0000b. 30:24 Reserved RsvdP Not Support. PI7C9X2G304EL Page 48 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 48: Vpd Data Register - Offset 60H (Upstream Port Only)

    When asserted, the user-defined replay time-out value is be employed. The Enable User Replay default value may be changed by SMBus or auto-loading from EEPROM. T imer Reset to 0b. PI7C9X2G304EL Page 49 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 49: Acknowledge Latency Timer - Offset 70H

    When clear, the frequency of releasing new credit to the link partner will be type oriented per update. Credit Update Mode T he default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0b. PI7C9X2G304EL Page 50 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 50: Switch Operation Mode - Offset 74H (Downstream Port Only)

    C_DRV_LVL_6P0_ EEPROM. 25:21 Reset to 1_0011b. T he default value may be changed by SMBus or auto-loading from C_DRV_LVL_6P0_ EEPROM. 30:26 Reset to 0_0010b. PI7C9X2G304EL Page 51 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 51: Xpip_Csr2 - Offset 78H

    15:13 Reserved RsvdP Not Support. T he default value may be changed by SMBus or auto-loading from P_DRV_LVL_MGN_ EEPROM. DELAT A_EN Reset to 0b. PI7C9X2G304EL Page 52 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 52: Xpip_Csr3 - Offset 80H

    T he default value may be changed by SMBus, I2C or auto-loading from EEPROM. DO_CHG_DAT A_ RAT E_CTRL Reset to 1b (Upstream port). Reset to 0b (Downstream ports). PI7C9X2G304EL Page 53 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 53: Tl_Csr - Offset 8Ch

    XPIP_CSR6 Reset to 79h. T he default value may be changed by SMBus or auto-loading from EEPROM. 25:24 REV_T S_CT R Reset to 00b. PI7C9X2G304EL Page 54 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 54: Phy Parameter 3 - Offset 90H

    SSID/SSVID CAPABILITY REGISTER – OFFSET B0h FUNCTIO N TYPE DESCRIPTIO N SSID/SSVID Read as 0Dh to indicate that these are SSID/SSVID capability registers. Capabilities ID PI7C9X2G304EL Page 55 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 55: Subsystem Vendor Id Register - Offset B4H

    State of GPIO [3] pin. 0b: GPIO [3] is an input pin GPIO [3] Output 1b: GPIO [3] is an output pin Enable Reset to 0b. PI7C9X2G304EL Page 56 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 56: Eeprom Control Register - Offset Bch (Upstream Port Only)

    EEPROM Command 1b: EEPROM write Reset to 0b. 1b: EEPROM acknowledge was not received during the EEPROM cycle. EEPROM Error Status Reset to 0b. PI7C9X2G304EL Page 57 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 57: Eeprom Address Register - Offset Bch (Upstream Port Only)

    SMBus or auto-loading Slot Implemented from EEPROM. Reset to the status of SLOT_IMP strapped pin. PI7C9X2G304EL Page 58 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 58: Device Capabilities Register - Offset C4H

    DEVICE CONTROL REGISTER – OFFSET C8h FUNCTIO N TYPE DESCRIPTIO N 0b: Disable Correctable Error Reporting Correctable Error 1b: Enable Correctable Error Reporting Reporting Enable Reset to 0b. PI7C9X2G304EL Page 59 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 59: Device Status Register - Offset C8H

    Asserted when fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Fatal Error Detected RW1C register. Reset to 0b. PI7C9X2G304EL Page 60 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 60: Link Capabilities Register - Offset Cch

    SMBus or auto-loading from EEPROM. 31:24 Port Number Reset to 00h for Port 0. Reset to 01h for Port 1. Reset to 02h for Port 2. PI7C9X2G304EL Page 61 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 61: Link Control Register - Offset D0H

    Indicates the negotiated width of the given PCIe link. Negotiated Link 25:20 Width Reset to 00_0010b (x2) (Upstream port). Reset to 00_0001b (x1) (Downstream ports). PI7C9X2G304EL Page 62 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 62: Slot Capabilities Register - Offset D4H (Downstream Port Only)

    Port to send the Set_Slot_Power_Limit message. The 14:7 Value default value may be changed by SMBus or auto-loading from EEPROM. Reset to 00h. PI7C9X2G304EL Page 63 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 63: Slot Control Register - Offset D8H (Downstream Port Only)

    0b: reset the power state of the slot (Power On) Power Controller 1b: set the power state of the slot (Power Off) Control Reset to 0b. Reserved RsvdP Not Support. PI7C9X2G304EL Page 64 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 64: Slot Status Register Offset D8H (Downstream Port Only)

    Reset to 1b. 17:12 Device Capabilities 2 Reset to 00h. T his field indicates if OBFF is supported. 19:18 OBFF Supported Reset to 01b. PI7C9X2G304EL Page 65 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 65: Device Control Register 2 - Offset E8H

    TYPE DESCRIPTIO N Current De- Reset to 0b (Upstream port). emphasis Level Reset to 1b (Downstream ports). 31:17 Link Status 2 Reset to 0000h. PI7C9X2G304EL Page 66 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 66: Slot Capabilities Register 2 - Offset F4H

    Completer Abort RW1CS Status Reset to 0b. When set, indicates that the Unexpected Completion event has occurred. Unexpected RW1CS Completion Status Reset to 0b. PI7C9X2G304EL Page 67 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 67: Uncorrectable Error Mask Register - Offset 108H

    When set, an event of ECRC Error has been detected is not logged in the Header Log register and not issued as an Error Message to RC either. ECRC Error Mask Reset to 0b. PI7C9X2G304EL Page 68 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 68: Uncorrectable Error Severity Register - Offset 10Ch

    Unsupported 1b: Fatal Request Error Severity Reset to 0b. 0b: Non-Fatal ACS violation 1b: Fatal severity Reset to 0b. 31:21 Reserved RsvdP Not Support. PI7C9X2G304EL Page 69 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 69: Correctable Error Status Register - Offset 110 H

    Advisory Non-Fatal Long register and not issued as an Error Message to RC either. Error Mask Reset to 1b. 31:14 Reserved RsvdP Not Support. PI7C9X2G304EL Page 70 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 70: Advance Error Capabilities And Control Register - Offset 118H

    VC belonging to the low-priority VC (LPVC) group. The default Low Priority value may be changed by auto-loading from EEPROM. Extended VC Count Reset to 000b. Reserved RsvdP Not Support. PI7C9X2G304EL Page 71 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 71: Port Vc Capability Register 2 - Offset 148H

    VC Arbitration Table after the bit of “Load VC Arbitration Table” is set. T able Status Reset to 0b. 31:17 Reserved RsvdP Not Support. PI7C9X2G304EL Page 72 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 72: Vc Resource Capability Register (0) - Offset 150H

    VC ID Reset to 000b. 30:27 Reserved RsvdP Not Support. 0b: disables this Virtual Channel 1b: enables this Virtual Channel VC Enable Reset to 1b. PI7C9X2G304EL Page 73 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 73: Vc Resource Status Register (0) - Offset 158H

    Bit 0 of this filed is read-only and must be set to “ 0” for the VC1. for bit0) T he default value may be changed by auto-loading from EEPROM. Reset to 00h. 15:8 Reserved RsvdP Not Support. PI7C9X2G304EL Page 74 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 74: 102 Vc Resource Status Register (1) - Offset 164H

    [23] [22] [21] [20] [19] [18] [17] [16] Phase Phase Phase Phase Phase Phase Phase Phase [31] [30] [29] [28] [27] [26] [25] [24] PI7C9X2G304EL Page 75 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 75: 104 Port Arbitration Table Register (0) And (1) - Offset 180H And 1C0H

    When 01h, it selects D0 Sustained power budget Other values would return zero power budgets, which means not supported Reset to 00h. 31:8 Reserved RsvdP Not Support. PI7C9X2G304EL Page 76 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 76: 107 Power Budgeting Data Register - Offset 214H

    Indicated the implements of ACS Source Validation. ACS Source Validation Reset to 1b. Indicated the implements of ACS T ranslation Blocking. ACS T ranslation Blocking Reset to 1b. PI7C9X2G304EL Page 77 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 77: 111 Egress Control Vector - Offset 228H (Downstream Port Only)

    Read as 0018h to indicate PCI Express Extended Capability ID for LTR 15:0 Extended Capability Extended Capability. Read as 1h. Indicates PCI-SIG defined PCI Express capability structure 19:16 Capability Version version number. PI7C9X2G304EL Page 78 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 78: 113 Max Snoop Latency Register - Offset 234H (Upstream Port Only)

    T his register provides a scale for the value contained within the Maximum Max No-Snoop No-Snoop Latency Value field 28:26 Latency Scale Reset to 000b 31:29 Reserved RsvdP Not Support. PI7C9X2G304EL Page 79 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 79: Clock Scheme

    PI7C9X2G304EL CLOCK SCHEME The built-in Integrated Reference Clock Buffer of the PI7C9X2G304EL supports three reference clock outputs. The clock buffer feature can be enabled and disabled by strapping the CLKBUF_PD pin. When CLKBUF_PD pin is asserted low, the clock buffer is enabled. The clock buffer distributes a single 100MHz reference clock input to three Reference Clock Output Pairs, REFCLKO_P[2:0] and REFCLKO_ N[2:0].

  • Page 80: Ieee 1149.1 Compatible Jtag Controller

    TEST_LOGIC_RESET state at power-up. PI7C9X2G304EL implements a 5-b it Instruction register to control the operation of the JTA G logic. The defined instruction codes are shown in the follo wing table. Those bit combinations that are not listed are equivalent to the BYPASS (11111) instruction.

  • Page 81: Bounda Ry Scan Register

    The boundary scan register has a set of serial shift-reg ister cells. A chain of boundary scan cells is fo rmed by connected the internal signal of the PI7C9X2G304EL package pins. The VDD, VSS, and JTA G pins are not in the boundary scan chain.
  • Page 82 Ball Location Type Tri-state Control Ce ll Internal Internal Control Internal CLKBUF_PD AP28 Birdir Internal Internal Internal EECLK AL35 Output2 EEPD AH34 Birdir Control PI7C9X2G304EL Page 83 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 83: Power Management

    The PI7C9X2G304EL supports D0, D1, D2, D3-hot, and D3-cold Power States. The PCI Exp ress Physical Link Layer of the PI7C9X2G304EL device supports the PCI Express Lin k Power Management with L0, L0s, L1, L2/ L3 ready and L3 Power States.

  • Page 84: Power Sequence

    Aux and Main power rails. Figure 11-1 Initial Power-Up Sequence Power-down sequence is the reverse of power-up sequence. PI7C9X2G304EL Page 85 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 85: Electrical And Timing Specifications

    Table 12-3 PCI Express Interface - Differential Transmitter (TX) Output (5.0 Gbps) Characteristics Parameter Symbol Unit Unit Interval 199.94 200.0 200.06 Differential p-p TX voltage swing TX-DIFF-P-P PI7C9X2G304EL Page 86 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 86 Table 12-5 PCI Express Interface - Differential Receiver (RX) Input (5.0 Gbps) Characteristics Parameter Symbol Unit Unit Interval 199.94 200.0 200.06 Differential RX Peak-to-Peak Voltage 1200 RX-DIFF-PP-CC T otal jitter tolerance 0.68 PI7C9X2G304EL Page 87 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 87: Operating Ambient Temperature

    - Ambient T emperature at 25 - Power consumption in the table is a reference, be affected by various environments, bus traffic and power supply etc. PI7C9X2G304EL Page 88 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 88: Package Information

    PI7C9X2G304EL PACKAGE INFORMATION The package of PI7C9X2G304EL is a 10mm x 10mm aQFN (136 Pin) package. The fo llo wing are the package information and mechanical dimension: Figure 13-1 Package outline drawing PI7C9X2G304EL Page 89 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 ©...

  • Page 89: Pi7C9X2G304El

    PI7C9X2G304EL Figure 13-2 Package bottom view PI7C9X2G304EL Page 90 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...

  • Page 90: Ordering Information

    10mm x 10mm PI 7C 9X2G304EL ZXA E X Tape & Reel Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family Pericom PI7C9X2G304EL Page 91 of 90 September 2017 www.diodes.com Document Number DS39931 Rev 2-2 © Diodes Incorporated...
  • Page 91 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Diodes Incorporated PI7C9X2G304ELZXAE PI7C9X2G304ELZXAEX PI7C9X2G304ELQZXAEX PI7C9X2G304ELQZXAE PI7C9X2G304EVAEVB-X1U...

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