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SD-AT50H
IC101 VHiCS493264-1: DSP (CS493264) (3/3)
Pin No.
Terminal Name
43
SCLK
44
MCLK
DATA7, EMDA7, GPIO7
DATA6, EMDA6, GPIO6
DATA5, EMDA5, GPIO5
DATA4, EMDA4, GPIO4
DATA3, EMDA3, GPIO3
DATA2, EMDA2, GPIO2
DATA1, EMDA1, GPIO1
DATA0, EMDA0, GPIO0
Input/Output
Input
Input
6
5
A0, SCCLK
7
8
9
10
11
VD2
12
DGND2
13
14
15
16
17
18
19
Figure 46 BLOCK DIAGRAM OF IC
Bidirectional digital-audio output bit clock. SCLK can be an output that is derived
from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the
MCLK rate and the digital-output configuration. SCLK can also be an input and
must be at least 48 Fs or greater. As an input, SCLK is independent of MCLK.
Bidirectional master audio clock. MCLK can be an output from the CS493XX that
provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs.
MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to
derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS493XX.
4
3
2
1
44
43
42
IC101
CS493264
20
21
22
23
24
25
26
– 46 –
Function
41
40
39
AUDATA2
38
DC
37
DD
36
RESET
AGND
35
34
VA
33
FILT1
32
FILT2
31
CLKSEL
30
CLKIN
29
CMPREQ, LRCLKN2
27
28
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