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3-5-4 Processor and Memory Module Matrix Table
Memory Q'ty
for each CPU
B0 B1 A0 A1 D0 D1 C0 C1 G1 G0 H1 H0 E1 E0 F1 F0
1 DIMM
V
2 DIMM
V
4 DIMM
V
6 DIMM
V
V
8 DIMM
V
V
12 DIMM
V
V
16 DIMM
V
V
V
NOTE!
l There should be at least one DDR4 DIMM per socket.
l If only one DIMM is populated in a channel, then populate it in the slot furthest away from CPU of that channel.
l Channel 0's on each memory controller (A/E/C/G, I/M/K/O) must be populated with same total capacity per channel (if populated).
l Channel 1's on each memory controller (B/F/D/H, J/N/L/P) must be populated with same total capacity per channel (if populated).
CPU0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
J0 J1 I0 I1 L0 L1 K0 K1 O1 O0 P1 P0 M1M0 N1 N0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
- 31 -
CPU1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
System Hardware Installation
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
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