Pin/Ball Descriptions - Sharp 32LF-94EC Service Manual

Micron® (0x2Ch)
• Industry-standard pinout
• Inputs and outputs are fully TTL-compatible
• Common Flash Interface (CFI) and Scalable
Command Set
• Automatic write and erase algorithm
• 5.6µs-per-byte effective programming time using write buffer
• 128-bit protection register
64-bit unique device identifier
64-bit user-programmable OTP cells
• Enhanced data protection feature with VPEN = VSS
Flexible sector locking
Sector erase/program lockout during power transition
•Security OTP block f feature
Permanent block locking (Contact factory for availability)
• 100,000 ERASE cycles per block
• Automatic suspend options:
Block Erase Suspend-to-Read
Block Erase Suspend-to-Program
Program Suspend-to-Read

12.6.3.Pin/Ball Descriptions

56-PIN TSOP 64-BALL FBGA
NUMBERS NUMBERS
55 G8
14, 2, 29 B4, B8, H1
16 D4
54 F8
32, 28, 27, 26, G2, A1, B1, C1,
25, 24, 23, 22, D1, D2, A2, C2,
20, 19, 18, 17, A3, B3, C3, D3,
13, 12, 11, 10, C4, A5, B5, C5,
8, 7, 6, 5, 4, 3, D7, D8, A7, B7,
1, 30 C7, C8, A8, G1
31 F1
15 A4
AK53 D.O.C. Service Manual
SYMBOL TYPE
WE# Input Write Enable: Determines if a given cycle is a WRITE
cycle. If WE# is LOW, the cycle is either a WRITE to the
command execution logic (CEL) or to the memory array.
Addresses and data are latched on the rising edge of the
WE# pulse.
CE0, CE1, Input Chip Enable: Three CE pins enable the use of multiple
CE2 Flash devices in the system without requiring additional
logic. The device can be configured to use a single CE
signal by tying CE1 and CE2 to ground and then using
CE0 as CE. Device selection occurs with the first edge of
CE0, CE1, or CE2 (CEx) that enables the device. Device
deselection occurs with the first edge of CEx that disables
the device (see Table 4 on page 14).
RP# Input Reset/Power-Down: When LOW, RP# clears the status
register, sets the ISM to the array read mode, and places
the device in deep power-down mode. All inputs, including
CEx, are "Don't Care," and all outputs are High-Z. RP#
must be held at VIH during all other modes of operation.
OE# Input Output Enables: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
A0 _ A21/ Input Address inputs during READ and WRITE operations. A0 is
(A22) only used in x8 mode and will be a NC in x16 mode (the
(A23) input buffer is turned off when BYTE = HIGH). A22 (pin 1,
ball A8) is only available on the 64Mb and 128Mb devices.
A23 (pin 30, ball G1) is only available on the 128Mb
device.
BYTE# Input BYTE# low places the device in the x8 mode. BYTE# high
places the device in the x16 mode and turns off the A0
input buffer. Address A1 becomes the lowest order
address in x16 mode.
VPEN Input Necessary voltage for erasing blocks, programming data,
or configuring lock bits. Typically, V
VCC. When V
protect.
16
DESCRIPTION
PEN
_ V , this pin enables hardware write
PEN PENLK
is connected to
22/03/2004