Gpio Output Data Register - Offset 65H - PEP CP390 Manual

CP390

4.2.6.3 GPIO Output Data Register - Offset 65h

This section describes the GPIO output data register.
Dword address = 64h
Byte enable p_cbe_1<3:0> = xx0xb
Table 4-5: GPIO Output Data Register - Offset 65h
Dword Bit
GPIO output
11:8 enable write-
1-to-clear
GPIO output
15:12 enable write-
1-to-set
Page 4 - 8
Name R/W
R/W1TC
R/W1TS
® PEP Modular Computers GmbH
Description
The gpio<3:0> pin output data
write-1-to-clear. Writing 1 to any of these bits drives
the corresponding bit low on the gpio<3:0> bus if it is
programmed as bi-directional. Data is driven on the
PCI clock cycle following completion of the
configuration write to this register. Bit positions cor-
responding to gpio pins that are programmed as input
only are not driven.
Writing 0 to these bits has no effect.
When read, reflects the last value written.
Reset value: 0.
The gpio<3:0> pin output data
write-1- to-set. Writing 1 to any of these bits drives
the corresponding bit high on the gpio<3:0> bus if it
is programmed as bi-directional. Data is driven on the
PCI clock cycle following completion of the
configuration write to this register. Bit positions cor-
responding to gpio pins that are programmed as input
only are not driven.
Writing 0 to these bits has no effect.
When read, reflects the last value written.
Reset value: 0.
Hotswap
ID 19976, Rev. 0200