Panasonic SA-PTX7P Service Manual page 146

SA-PTX7P
SCHEMATIC DIAGRAM - 14
B
DIGITAL CIRCUIT
:+B SIGNAL LINE
B114
B110
B119
B115
B117
B113
CN1503
1
A
TO
DVD MODULE
NT_PL_OUT
(FPGA) CIRCUIT
(P3007)
IN SCHEMATIC
SH_SCRCLK
DIAGRAM - 6
SH_SCRCE
SH_SCRTXD1
SH_SCRRXD1
FPGA_MEM1
CONFIG_CLK
CONFIG_TX
FPGA_DONE
50
B120
B118
B121
B116
B111
29 30
:DIGITAL AUDIO SIGNAL LINE :DIGITAL AUDIO REC SIGNAL LINE
TO DIGITAL
SECTION (3/6)
DGND 50
LCDD0
LCDD0 49
LCDD1
LCDD1 48
LCDD2
LCDD2 47
LCDD3
LCDD3 46
LCDD4
BIT_CLK0
LCDD4 45
LCDD5
LCDD5 44
LCDD6
BIT_CLK_Z0
LCDD6 43
LCDD7
LCDD7 42
LCDD8
LCDD8 41
LCDD9
LCDD9 40
LCDD10
LCDD10 39
LCDD11
LCDD11 38
LCDD12
LCDD12 37
LCDD13
CD_SEL
LCDD13 36
LCDD14
DV5_DMIX
LCDD14 35
LCDD15
LCDD15 34
DGND 33
AKDT
LB1923 LCD_CLK
DV5_LRCK
LCDCLK 32
J0JCC0000103
DGND 31 AKLRCK
LB1924 LCDCL2
LCD_CL2 30
J0JCC0000103
DGND 29
LCDCL1
LCD_CL1 28
LCDFLM
AKSCLK
LCD_FLM 27
DV5_SCLK
LCD_DON
LCD_DON 26
NT_PL_OUT
25
NC_1
NC 24
DGND 23
SH_SCRCLK1
22
DGND 21
SH_SCRCE
20
SH_SCRTXD1 AKDT
19
SH_SCRRXD1
18
DGND 17
NT_PL_IN
NT_PL_IN 16
FPGA_MEM1
15
DGND 14
FPGA_CONF_CLK
13
DGND 12
FPGA_CONF_TX
11
FPGA_PROG
PROGRAM 10 AKLRCK
FPGA_DONE
9 AKSCLK
FPGA_INIT
FPGA_INIT 8
DGND 7
DV5_SCLK
SRCK 6
DV5_LRCK
LRCK 5
DV5_DMIX
DMIXOUT 4
DV5_ON
DGND 3
DGND 2
DGND 1
32 33 34
:MAIN SIGNAL LINE
IC1905 IC1905
C0JBAR000434
2 - CH MULTIPLEXER
VCC
IC1901 1 A 8
C0JBAR000434 2 B STB 7
2 - CH MULTIPLEXER 3 Y SEL 6
4 GND 5
Y
IC1920
C0JBAR000434
2 - CH MULTIPLEXER
IC1901
IC1920
1 A VCC 1 A VCC
8 8
J0JBC0000014
2 B 2 B
STB 7 STB 7
Y
3 SEL 6 3 Y SEL 6
4 GND Y 5 4 GND Y 5 J0JBC0000014
R1936 10K R1907 10K
LB1903 J0JBC0000014
IC1907 IC1902
C0JBAZ000851
C0FBBK000049
BUS BUFFER 2 - CH AUDIO D/A CONVERTER
R1916
1
1OE VCC 14 1 ZEROL/NA 16
100
PCMMS C1903 10V10
2 1A 4OE 13 2 MS VoutL 15
PCMMC C1904 10V10
3 1Y 4A 12 3 MC VoutR 14
PCMMD C1905 10V10
R1920 4 2OE 4Y 11 4 MD Vcom 13
100
5
5 2A 3OE 10 SCK AGND 12
PCMDT
6 2Y 3A 9 6 DATA Vcc 11
PCMBCK
7 GND 3Y 8 7 BCK 10
NC
PCMLRCK
LRCK
8 NC 9
R1921
100
R1923
100
IC1903
C1917 0.1
C0FBAK000026
2 - CH AUDIO A/D CONVERTER
R1901
R1926 SW_AKDT
33 C1907
33
0.1
9 SDTO DGND 8
4 GND 3
R1902 33
10 7
LRCK VD
Y
C1908
C1912
11 6
MCLK VA
2 0.1 10V10
R1903 33
A
12 5
SCLK AGND
R1908
13 C1902
PDN VCOM 4 10K
5 1
R1904 10K 0.47
VCC
OE 14
DIF CKS1 3
R1905 10K C1909 10V10
IC1906
15 CKS2 AINL 2
R1906 10K C1910
10V10
C0JBAZ002262
16 CKS0 AINR 1
3 - STATE BUFFER
C1900 0.1 IC1900
R1900 C0JBAA000494
33
AND GATE
GND
4 3
AKRST
2
TO DIGITAL PRESTN
5 VCC 1
SECTION (5/6)
35 36 37
146
X1901
H0J150500006
15MHz
R1924
1M
IC1904
IC1904
R1918
LB1902 390 C0JBAB000837
4 3 INVERTER
VCC
5 2
C1915 GND
LB1901
0.1
6 1
R1915 1M
R1922
390
X1900
H0J123500005
12.288MHz
R1912 1K L_OUT
R1913 1K R_OUT
R_IN
L_IN
R_OUT
R1910 100 L_IN
R_IN
R1911 100 L_OUT
C1930
0.1
R1930
10K
GND
4 3 1/6
2
4/6
VCC
5 1
NC
IC1918
C0JBAB000884
SCHMITT INVERTER
38 39
I
J
K
L
CN1900
1
28 NC
27 NC
LB1904 J0JBC0000014
26 SUBI03
M
25 SUBI02
LB1906 J0JBC0000014
SUBI01
24
23 D_GND
22 SH_RXD
21 D_GND
33
R1919
20 SH_TXD
19 D_GND
18 SD_OPEN
LB1910 J0JBC0000014
17 SH_RSTN
D
LB1922 J0JBC0000014
16 SEL
TO
LB1921 J0JBC0000014
15 DCDET
MAIN CIRCUIT
LB1915 J0JBC0000014
(CN502)
14 ADIN_R
IN SCHEMATIC
13 A_GND
LB1916 J0JBC0000014
DIAGRAM - 16
12 ADIN_L
N
11 A_GND
LB1917 J0JBC0000014
10 DACOUT_R
9 A_GND
LB1918 J0JBC0000014
8 DACOUT_L
LB1919
J0JGC0000050
7 A5V
LB1911 J0JGC0000050
6 D3.3V
LB1912 J0JGC0000050
5 D3.3V
LB1913
J0JGC0000050
4 D3.3V
3 3.3V_GND
3.3V_GND
2
1 3.3V_GND 28
O
2/6 3/6
5/6 6/6
SA-PTX7P DIGITAL CIRCUIT
P
40 41 42