Panasonic SA-PM30MD Service Manual page 30

Md stereo system
Table of Contents

Advertisement

SA-PM30MD
Pin
Mark
No.
24
ECM
25
ECS
26
KICK
27
TRD
28
FOD
29
VREF
30
FBAL
31
TBAL
32
FE
33
TE
34
RFENV
35
VDET
36
OFT
37
TRCRS
38
/RFDET
39
BDO
40
LDON
41
PLLF2
42
TOFS/DSLF2
43
DRF
44
ARF
45
IREF
46
DRF
47
DSLF
48
PLLF
49
VCOF
50
AVDD2
51
AVSS2
52
EFM
53
PCK
54
VCOF2
12.8. IC703 (BA5948FPE2) Focus Coil / Tracking Coil / Traverse Motor /
Spindle Motor Driver
Pin
Mark
No.
1
IN2
2
PC2
3
IN1
4
PC1
5
NC
I/O
Function
O
Spindle Motor Drive Signal
Output (Forced Mode Output)
O
Spindle Motor Drive Signal
Output.
(Servo Error Signal Output)
O
Kick Pulse Output
O
Tracking Drive Output
O
Focus Drive Output
I
D/A (Drive) Output (TVD, ECS,
TRD, FOD, FBAL, TBAL)
Reference Voltage Input
O
Focus Error Signal Input
(Analog Input)
O
Tracking Balance Adjustment
Output
I
Focus Error Signal Input
(Analog Input)
I
Tracking Error Signal Input
(Analog Input)
I
RF Envelope Signal Input
I
Vibration Detection Signal Input
("H": Detect)
I
Off-Track Signal Input
("H": Off Track)
I
Track Cross Signal Input)
I
RF Detection Signal Input
("L": Detect)
I
Dropout Signal Input
("H": Dropout)
O
Laser on Signal Output
("H": ON)
I/O
PLL Loop Filter Characteristic
Switching Terminal
O
Tracking Offset Alignment
Output/ DSL Balance Output
(DA Output)
O
Double Speed Status Signal
Output
("H":DS)
I
RF Signal Input
I
Reference Current Input
I
DSL Bias Terminal
I/O
DSL Loop Filter
I/O
PLL Loop Filter
I/O
VCO Loop Filter Terminal
I
Power Supply Input (For Analog
Circuit)
I
GND (For Analog Circuit)
O
EFM Signal Output (Not Used,
Open)
O
PLL Extraction Clock Output
(Not Used, Open)
(fPCK= 4.3218 MHz during
Normal Playback)
I/O
VCO loop Filter for 33.8688
MHz Conversion Terminal for
16.9344 Mhz Crystal mode,
Must use other Circuit)
I/O
Function
I
Motor Driver 92) Input
I
Turntable Motor Drive Signal
("L":ON)
I
Motor Driver (1) Input
Traverse Motor Drive Signal
("L":ON)
No connection
Pin
Mark
I/O
No.
55
SUBC
56
SBCK
57
VSS
58
X1 IN
59
X2 OUT
60
VDD
61
BYTCK
62
/CLDCK
63
FCLK
64
IPFLAG
65
FLAG
66
CLVS
67
CRC
68
DEMPH
69
RESY
70
IOSEL
71
/TEST
72
AVDD1
73
OUTL
74
AVSS1
75
OUTR
76
RSEL
77
IOVDD
78
PSEL
79
MSEL
80
SSEL
Pin
Mark
I/O
No.
6
NC
7
NC
8
NC
9
PGND1
10
PVCC1
11
D1-
30
Function
O
Sub-Code Serial Data Output
(Not Used, Open)
I
Clock Input for Sub-Code Serial
Data)
I
GND
I
Crystal Oscillating Circuit Input
(f= 16.9344 MHz)
O
Crystal Oscillating Circuit Input
(f= 16.9344 MHz)
I
Power Supply Input (For
Oscillating Circuit)
O
Byte Clock Output (Not Used,
Open)
O
Sub-Code Frame Clock Signal
Output
(fCLDCK= 7.35 kHz During
Normal Playback)
O
Crystal Frame Clock Signal
Output)
(fCLDCK= 7.35 kHz)
O
Interpolation Flag Output
("H": Interpolation) (Not Used,
Open)
O
Flag Output (Not Ised, Open)
O
Spindle Servo Phase
Synchronizing Signal Output
("H": CLV, "L": Rough Servo)
(Not used, Open)
O
Sub-Code CRC Checked
Output
("H": OK, "L" NG) (Not Used,
Open)
O
De-Emphasis DN Signal Output
("H":ON)
O
Frame Re-synchronizing Signal
Output
I
Mode Switching Terminal
I
Test Input
I
Power Supply Input (For Analog
Circuit)
O
Left Channel Audio Signal
Output
I
GND
O
Right Signal Audio Signal
Output
I
RF Signal Polarity Assignment
Input
(at "H" level, RSEL= "H", at "L"
SEL= "L")
I
5V Supply
I
Test terminal (Connected to
GND)
I
SMCK Oscillating Frequency
Designation Input
("L": 4.2336 MHz, "H"
8.4672MHz)
I
SUBQ Output Mode Select
("H": Q-Code Buffer Mode)
Function
No connection
No connection
No connection
Ground Conenction (1) for Driver
I
Power Supply (1) for Driver
O
Motor Driver (1) reverse - action
output

Advertisement

Table of Contents
loading

Table of Contents