Casio WK-1800 Service Manual page 14

CPU (LSI9: HD6433048SA89F)
The 16 bit CPU contains a 1M-bit ROM, a 16K-bit RAM, eleven 8-bit I/O ports, an A/D converter, a D/A
converter and serial interfaces. The CPU accesses to the RAM1, RAM2, DSP, Key controller, FDD control-
ler and LCD driver LSI. The CPU also controls buttons, LEDs, bender input and MIDI input/output.
Pin No. Terminal
1 VCC
2 ~ 5 PB0 ~ PB3
6 PB4
7 PB5
8 DREQ0
9 PB7
10 RES0
11 VSS
12 TXD0
13, 15 ~ 17 P91, P93~P95
14 RXD0
18 ~ 21
D0 ~ D15
23 ~ 34
22 VSS
35 VCC
36 ~ 43,
A0 ~ A19
45 ~ 56
44, 57 VSS
55, 59, 60 P52, P61, P62
58 WAIT
61 CLKOUT
62 STBY
63 RES
64 NMI
65 VSS
66, 67 EXTAL, XTAL
68 VCC
69 AS
70 RD
71 HWR
72 LWR
73 ~ 75 MD0 ~ MD2
76, 77 AVCC, VREF
78 P70
79 AN1
In/Out
In VCC (5 V) source.
Out Data bus for LCD driver.
Out Chip enable signal for LCD driver.
Out Read/write signal for LCD driver.
— DMA (Direct Memory Access) request.
Out Register selection signal for LCD driver.
In Not used.
In Ground terminal (0 V).
Out MIDI signal output.
In Key input signal from buttons.
In MIDI signal input.
In/Out Data bus.
In Ground terminal (0 V).
In Vcc (5 V) source.
Out Address bus.
In Ground terminal (0 V).
In Key input signal from buttons.
— Not used.
Out Clock signal (16 MHz).
— Not used.
In Reset signal at VDD (5 V) supplied.
In Power ON signal input.
In Ground terminal (0 V).
In Clock (16 MHz) input.
In Vcc (5 V) source.
— Not used.
Out Read signal.
Out Write signal for upper data bus.
Out Write signal for lower data bus.
In Mode selection terminals.
In Power source and reference voltage for internal A/D, D/A.
In Key input signal from buttons.
In Pitch bender voltage detection.
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Function