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3.4 Clocks
3.4 Clocks
There are two major time bases in the MT6255. For the faster one is the 26 MHz clock originated from the
digital control oscillator(DCXO) of RF block. This is then converted to the square-wave signal through
CLKSQ.
The other time base is the 32768 Hz clock generated by an on-chip oscillator connected to an external
crystal.
26MHz
DCXO
CLKSQ
1/2
MPLL
UPLL
32KHz
XOSC_ANA
DVDD28_IO
(VIO_2V8)
LGE Internal Use Only
LGE Internal Use Only
CLKSQ_DIV2_MCU_SEL0
1/2
CLKSQ_26M_CK
CLKSQ_DIV2_MCU_SEL0
CLKSQ_CON (Cx8300_0100)
MPLL_113M_CK
PLL_CON0(Cx8300_0200)
PLL_CON1(Cx8300_0204)
CLKSQ_DIV2_GSM_SEL0
(Cx8300_0100[2])
MPLL_CON0(Cx8300_0210)
MPLL_CON1(Cx8300_0214)
UPLL_CON0(Cx8300_0208)
UPLL_CON1(Cx8300_020C)
UPLL_104M_CK
CLKSQ_DIV2_USB_SEL0
USB PHY
UPLL_48M_USB_CK
UPLL_48M_IRDA_CK
XOSOOUT
XOSQ_CON (Cx8300_0000)
Figure. 3.4.1 Clock distributions inside the MT6255.
MT6255
MT6255
Figure. 3.4.2 Crystal Oscillator External Connection
Figure. 3.4.2 Crystal Oscillator External Connection
MPLL_SEL
(Cx8300_0204[1:0])
0
(Cx8300_0100[0])
2
3
FMCU_CK
0
1
(Cx8300_0100[1])
DPLL_SEL
(Cx8300_0204[3:2])
0
1
0
2
FDSP_CK
3
GPLL_SEL
(Cx8300_0204[4])
0
0
1
FGSM_CK
1
UPLL_SEL
(Cx8300_0100[3])
(Cx8300_0204[5])
0
0
1
FUSB_CK
1
USB_PHY_CLK
F48M_CK
F32k_CK
B15
XOUT
A15
XIN
C15
TESTMODE
2
1
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3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
EN
CG
104MHz EMI clock
104MHz AHB clock
52MHz AHB clock
52MHz APB clock
MCV_DCM
EN
CG
10MHz GDSP1_CK
10MHz GDSP2_CK
DSP_DCM
EN
52MHz GGSM_CK
CG
52MHz BFE_clock
GSM_DCM
EN
CG
GUSB_CK
USB_DCM
MSDC_DCM
EN
MSDC_clock
CG
IrDA_clock
EN
CG
SLOW_CK
SLOW_DCM
X102
1
2
32.768KHz
FC-135
2
C144
C145
22p
22p
1
Only for training and service purposes
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