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Chapter 4 Mtlc Demonstrations; System Requirements; Painter Demonstration - Terasic P0158 User Manual

Capacitive multi-touch lcd with camera module

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This chapter gives detailed description of the provided bundles of exclusive demonstrations
implemented on the DE2-115 development board with MTLC. These demonstrations are
particularly designed (or ported) for MTLC, with the goal of showing the potential capabilities
of the kit and showcase the unique benefits of FPGA-based SOPC systems such as reducing
BOM costs by integrating powerful graphics and video processing circuits within the FPGA.
Please notice that all the demonstrations in this chapter are using the DE2-115
development board with MTLC. For the demonstrations with other FPGA board can be
found on MTLC system CD.
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To run and recompile the demonstrations, you should:
Install Altera Quartus II 13.1 and NIOS II EDS 13.1 or later edition on the host computer
Install the USB-Blaster driver software. You can find instructions in the tutorial "Getting
Started with Altera's DE2-115 Board" (tut_initialDE2-115.pdf) which is available on the
DE2-115 system CD
Copy the entire \Demonstration\DE2-115 folder from the MTLC system CD to your host
computer
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This chapter shows how to control LCD and touch controller to establish a paint demo based on
SOPC Builder and Altera VIP Suite. The demonstration shows how multi-touch gestures and
single-touch coordinates operate.
Figure 4-1
shows the hardware system block diagram of this demonstration. For LCD display
processing, the reference design is developed based on the Altera Video and Image Processing Suite
(VIP). The Frame Reader VIP is used for reading display content from the associated video memory,
and VIP Video Out is used to display the display content. The display content is filled by NIOS II
processor according to users' input.
For multi-touch processing, a Terasic Memory-Mapped IP is used to retrieve the user input,
including multi-touch gesture and single-touch coordinates. Note, the IP is encrypted, so the license
should be installed before compiling the Quartus II project. For IP--usage details please refer to the
MTLC User Manual
MTLC Demonstrations
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Chapter 4
www.terasic.com
May 22, 2014

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