Zenith Presentation Series Service Manual page 48

One of the operational amplifiers of IC4100 (pins 1,2,
& 3) provides the error voltage needed to regulate the
B++ output voltage to a specified level. This voltage is
dependent on the horizontal scanning frequency and
is determined by the Deflection Processor (ICX2600 in
Main Chassis). A corresponding level 0 or 9 Vdc level
(NTSC or SVGA mode) is sent to pin 7 of connector 4G2
(F0 signal). The F0 signal switch Q4100 adjusts the
feedback path to have a B++ range of approximately 50
to 65 Vdc in NTSC mode and approximately 120 to 145
Vdc in SVGA mode. This depends on the EW-DRV level
from the same processor (Screen Size Control).
This circuit also receives a pincushion and size
correction signal. EW-DRV from the Deflection Processor
(ICX2600), Pin 4 of connector 4V2, modulates B++ to
provide keystone and pincushion geometric correction.
EW-DRV is a vertical deflection rate parabola.
The Change Mode Protection is accomplished by the
other operational amplifier in IC4100 (pins 13, 14, &
3). This protection is provided by comparing the FH-
STAT signal from the Deflection Processor (ICX2600),
pin 8 of connector 4G2, with a 5 Vdc level. When a
change mode is performed (from NTSC to SVGA or vice
versa), the FH-STAT signal goes to low level forcing the
Scan Boost to work in a minimum mode (minimum B++)
to minimize the change mode transients.
BASE DRIVE
The Base Drive (Proportional Drive) circuit provides high
forward and reverse current to drive the base of the
Horizontal Output Transistor QX3200, from a low level
input (H-DRV from the Deflection Processor, ICX2600,
in Main Chassis) at pin 1 of connector 4H2. This signal
is approximately 9 volts peak at the operating frequency
and has a duty cycle of about 40% high, 60% low.
Base Driver
+15V
R4002
C4000
H-DRV R4000
IN Q4000
R4001
0
0
SR23 - 923-03509
CIRCUIT OVERVIEW (continued)
+15V
R4004
C4001 C4002
R4005
D4000
R4003
Q4001
0
0
0
Current from H-DRV is amplified by transistor Q4002
and Q4003, providing a low impedance to rapidly drive
the gate of the drive transistor, Q4004. This action
results in and CX3204 are always connected in the
circuit. CX3205 is switched by Q3202 via F0 signal (pin
7 of connector 4H2) from the Deflection Processor,
ICX2600, in Main Chassis. This signal is buffered by
Q3201. At NTSC mode all capacitors are switched in,
and at SVGA mode only CX3203 and CX3204 are switched
in.
S-CAPACITOR SWITCHING
The "S" shaping capacitors, CX3203, CX3204 and
CX3205, provide the proper deflection current for
optimum raster linearity with the two frequencies. As
the horizontal scanning frequency increases, less capacity
is needed. CX3203 and CX3204 are always connected in
the circuit. CX3205 is switched by Q3202 via F0 signal
(pin7 of connector 4H2) from the Deflection Processor,
ICX2600, in Main Chassis. The signal is buffed by Q3201.
At NTSC mode all capacitors are switched in, and at
SVGA mode only CX3203 and CX3204 are switched in.
HV COMPENSATION
The flyback pulse voltage (H-FLYBK) from pin 6 of T3201
(Flyback Transformer) is peak detected (rectified) by
the diode D2901 and capacitor C2900. This forms a DC
voltage appearing on C2900 representative of the CRT
anode voltage produced by T3201. This voltage is used
in one of the operational amplifiers of IC3201 to provide
the error voltage needed to regulate the HV to a specified
level.
+22V
RX4010
C4003 C4004
0
0
+15V
RX4006
Q4002
Q4004
R4008
R4011
R4009
Q4003 C4005
0 0
RX4007
0
0
3-10
D4001
HOT BASE
RX4012
RX4013 RX4014
L2
HOT EMITTER
0 0
L1
L3
0
CS - SERVICING
OUT
OUT