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Exar XRT86VL30 Manual

Single t1/e1/j1 framer/liu combo - t1 register description
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SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2008
GENERAL DESCRIPTION
The XRT86VL30 is a single channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
3
solution
featuring
R
Reconfigurable,
Redundancy).
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86VL30
provides protection from power failures and hot
swapping.
The XRT86VL30 contains an integrated DS1/E1/J1
framer and LIU which provides DS1/E1/J1 framing
and error accumulation in accordance with ANSI/
ITU_T specifications. The framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
The Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit
HDLC
controllers
contents of the Transmit HDLC buffers into LAPD
Message frames. There are 3 Receive HDLC
controllers which extract the payload content of
F
1. XRT86VL30 S
IGURE
Local PCM
XRT86VL30
Highway
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
System (Terminal) Side
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
technology
(Relayless,
The
physical
which
encapsulate
C
DS1 (T1/E1/J1) F
INGLE
HANNEL
Tx Overhead In
2-Frame
Tx Serial
Slip Buffer
Data In
Elastic Store
2-Frame
Rx Serial
Slip Buffer
Data Out
Elastic Store
PRBS
Performance
Generator &
Monitor
Analyser
Signaling &
JTAG
Alarms
INT
TxON
Memory
Receive LAPD Message frames from the incoming
T1/E1/J1 data stream and write the contents into the
Receive HDLC buffers. The framer also contains a
Transmit and Overhead Data Input port, which
permits Data Link Terminal Equipment direct access
to the outbound T1/E1/J1 frames.
Receive Overhead output data port permits Data Link
Terminal Equipment direct access to the Data Link
bits of the inbound T1/E1/J1 frames.
The XRT86VL30 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions
include
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
APPLICATIONS AND FEATURES (NEXT PAGE)
/LIU C
RAMER
OMBO
External Data
Link Controller
Rx Overhead Out
Tx LIU
Tx Framer
Interface
LLB
LB
Rx LIU
Rx Framer
Interface
LIU &
HDLC/LAPD
Loopback
Controllers
Control
Microprocessor
DMA
Interface
Interface
4
3
µP
D[7:0]
A[11:0]
Select
Intel/Motorola µP
Configuration, Control &
Status Monitor
•
•
(510) 668-7000
FAX (510) 668-7017
XRT86VL30
REV. 1.0.0
Likewise, a
Loop-backs,
Boundary
1:2 Turns Ratio
TTIP
TRING
1:1 Turns Ratio
RTIP
RRING
RxLOS
Line Side
WR
ALE_AS
RD
RDY_DTACK
•
www.exar.com
scan,

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Summary of Contents for Exar XRT86VL30

  • Page 1 Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the The XRT86VL30 is a single channel 1.544 Mbit/s or Receive HDLC buffers. The framer also contains a 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated...
  • Page 2 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 APPLICATIONS • High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • T1/E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 •...
  • Page 3 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 • Remote Alarm Indication with Customer Installation (RAI-CI) • Gapped Clock interface mode for Transmit and Receive. • Intel/Motorola and Power PC interfaces for configuration, control and status monitoring •...
  • Page 4 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 LIST OF PARAGRAPHS 1.0 REGISTER DESCRIPTIONS - T1 MODE ....................9 2.0 LINE INTERFACE UNIT (LIU SECTION) REGISTERS ...............124...
  • Page 5 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 LIST OF FIGURES Figure 1.: XRT86VL30 2-channel DS1 (T1/E1/J1) Framer/LIU Combo ................1...
  • Page 6 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 LIST OF TABLES Table 1:: Register Summary .............................. 4 Table 2:: Clock Select Register(CSR) Hex Address: 0x0100 ..9 Table 3:: Line Interface Control Register (LICR) Hex Address: 0x0101 ....11 Table 4:: Framing Select Register (FSR) Hex Address: 0x0107 ....
  • Page 7 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 Table 59:: LAPD Buffer 1 Control Register (LAPDBCR1) Hex Address: 0x0700 ........78 Table 60:: PMON Receive Line Code Violation Counter MSB (RLCVCU) Hex Address: 0x0900 ....79 Table 61:: PMON Receive Line Code Violation Counter LSB (RLCVCL) Hex Address: 0x0901 ....
  • Page 8 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 Table 118:: LIU Channel Control Arbitrary Register 4 (LIUCCAR4) Hex Address: 0x0F0B ..... 141 Table 119:: LIU Channel Control Arbitrary Register 5 (LIUCCAR5) Hex Address: 0x0F0C ..... 141 Table 121:: LIU Channel Control Arbitrary Register 7 (LIUCCAR7) Hex Address: 0x0F0E .....
  • Page 9 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 DESCRIPTION OF THE CONTROL REGISTERS - T1 MODE All address on this register description is shown in HEX format. 1: R ABLE EGISTER UMMARY UNCTION YMBOL Control Registers (0x0100 - 0x01FF)
  • Page 10 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 1: R ABLE EGISTER UMMARY UNCTION YMBOL BERT Control & Status - Register 1 BERTCSR1 0x0123 Loopback Code Control Register - Code 0 LCCR0 0x0124 Transmit Loopback Code Register...
  • Page 11 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 1: R ABLE EGISTER UMMARY UNCTION YMBOL Transmit Signaling Control Register 0-23 TSCR 0-23 0x0340 - 0x0357 Receive Channel Control Register 0-23 RCCR 0-23 0x0360 - 0x0377 Receive User Code Register 0-23...
  • Page 12 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 1: R ABLE EGISTER UMMARY UNCTION YMBOL Interrupt Generation/Enable Register Address Map (0x0B00 - 0x0B41) Block Interrupt Status Register BISR 0x0B00 Block Interrupt Enable Register BIER 0x0B01 Alarm & Error Interrupt Status Register...
  • Page 13 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 1: R ABLE EGISTER UMMARY UNCTION YMBOL BOC Unstable Interrupt Status Register BOCUSR 0x0B74 BOC Unstable Interrupt Enable Register BOCUER 0x0B75 LIU Register Summary - Channel Control Registers LIU Channel Control Register 0...
  • Page 14 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 1.0 REGISTER DESCRIPTIONS - T1 MODE All address on this register description is shown in HEX format 2: C (CSR) 0100 ABLE LOCK ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION...
  • Page 15 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 2: C (CSR) 0100 ABLE LOCK ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1:0 CSS[1:0] Clock Source Select These bits select the timing source for the Transmit T1 Framer block.
  • Page 16 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 3: L (LICR) 0101 ABLE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FORCE_LOS Force Transmit LOS (To the Line Side) This bit permits the user to configure the transmit direction circuitry (within the channel) to transmit the LOS pattern to the remote terminal equipment, as described below.
  • Page 17 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 3: L (LICR) 0101 ABLE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Encode B8ZS Encode AMI or B8ZS/HDB3 Line Code Select This bit enables or disables the B8ZS/HDB3 encoder on the transmit path.
  • Page 18 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 4: F (FSR) 0107 ABLE RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Signaling update on Enable Robbed-Bit Signaling Update on Superframe Boundary Superframe Boundaries on Both Transmit and Receive Direction...
  • Page 19 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 4: F (FSR) 0107 ABLE RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FASTSYNC Faster Sync Algorithm This bit is used to specify one of the synchronization criteria that the Receive T1 Framer block employs.
  • Page 20 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 5: A (AGR) 0108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Yellow Alarm - One-Second Yellow Alarm Rule Enforcement One Second This bit is used to enforce the one-second yellow alarm rule according to the yel- Rule low alarm (RAI) transmission duration per the ANSI standards.
  • Page 21 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 5: A (AGR) 0108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 5-4 YEL[1:0] Yellow Alarm (RAI) Duration and Format The exact function of these bits depends on whether or not the one-second yellow alarm rule is enforced.
  • Page 22 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 5: A (AGR) 0108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 5-4 YEL[1:0] (Continued) ABLE YELLOW ALARM FORMAT WHEN ONE SECOND RULE IS ENFORCED YEL[1:0] ELLOW LARM...
  • Page 23 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 5: A (AGR) 0108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-2 Transmit AIS Transmit AIS Pattern Select[1:0]: Pattern These two bits permit the user to do the following.
  • Page 24 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 8: S MUX R (SMR) 0109 ABLE YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved MFRAMEALIGN Transmit Multiframe Sync Alignment This bit forces Transmit T1 framer block to align with the backplane multiframe boundary (TxMSYNC_n).
  • Page 25 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 8: S MUX R (SMR) 0109 ABLE YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Transmit Frame Sync Transmit Frame Sync Select Select This bit permits the user to configure the System-Side Terminal...
  • Page 26 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 8: S MUX R (SMR) 0109 ABLE YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CRC-6 Bits Source CRC-6 Bits Source Select Select This bit permits the user to specify the source of the CRC-6 bits, within the outbound T1 data-stream, as depicted below.
  • Page 27 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 9: T 010A (TSDLSR) ABLE RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved Reserved Reserved 5-4 TxDLBW[1:0] Transmit Data Link Bandwidth[1:0] These two bits are used to select the bandwidth for data link mes- sage transmission.
  • Page 28 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 9: T 010A (TSDLSR) ABLE RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxDL[1:0] Transmit Data Link Source Select [1:0] These two bits specify the source for data link bits that will be inserted in the outbound T1 frames.
  • Page 29 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 10: F (FCR) 010B ABLE RAMING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reframe Force Reframe A ‘0’ to ‘1’ transition will force the Receive T1 Framer to restart the syn- chronization process.
  • Page 30 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 11: R & D (RSDLSR) 010C ABLE ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved Reserved Reserved 5-4 RxDLBW[1:0] Receive Data Link Bandwidth[1:0]: These two bits select the bandwidth for data link message reception.
  • Page 31 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 11: R & D (RSDLSR) 010C ABLE ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 RxDL[1:0] Receive Data-Link Destination Select[1:0]: These bits specify the destination circuitry, that is used to process the Data-Link data, within the incoming T1 data-stream.
  • Page 32 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 12: R 010D (RSCR 0) ABLE ECEIVE IGNALING HANGE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Ch. 0 These bits indicate whether the Channel Associated signaling data, associated with Time-Slots 0 through 7 within the incoming T1 data- Ch.
  • Page 33 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 15: R (RIFR) 0112 ABLE ECEIVE RAME EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION In Frame In Frame State This READ-ONLY bit indicates whether the Receive T1 Framer block is currently declaring the “In-Frame”...
  • Page 34 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 16: D (DLCR1) 0113 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AutoRx Auto Receive LAPD Message This bit configures the Receive HDLC Controller Block #1 to discard any incoming BOS or LAPD Message frame that exactly match which is currently stored in the Receive HDLC1 buffer.
  • Page 35 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 16: D (DLCR1) 0113 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_FCS_EN Transmit LAPD Message with Frame Check Sequence (FCS) This bit permits the user to configure the Transmit HDLC Controller block # 1 to compute and append FCS octets to the “back-end”...
  • Page 36 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 17: T (TDLBCR1) 0114 ABLE RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxHDLC1 BUFAvail/ Transmit HDLC1 Buffer Available/Buffer Select BUFSel This bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below.
  • Page 37 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 18: R (RDLBCR1) 0115 ABLE ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RBUFPTR Receive HDLC1 Buffer-Pointer This bit Identifies which Receive HDLC1 buffer contains the most recently received HDLC1 message.
  • Page 38 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 19: S (SBCR) 0116 ABLE UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSB_ISFIFO Transmit Slip Buffer Mode This bit permits the user to configure the Transmit Slip Buffer to function as either “Slip-Buffer”...
  • Page 39 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 19: S (SBCR) 0116 ABLE UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SB_ENB(1) Receive Slip Buffer Mode Select These bits select modes of operation for the receive slip buffer. These two...
  • Page 40 1 =WR functions as a write strobe signal 4 - 3 Reserved Reserved DMA0_CHAN(2) Channel Select These three bits select which T1 channel within the XRT86VL30 uses DMA0_CHAN(1) the Transmit DMA_0 (Write) interface. 000 = Channel 0 DMA0_CHAN(0) 001 = Reserved...
  • Page 41 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 22: DMA 1 (R (D1RCR) 0119 ABLE ONFIGURATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 Reserved Reserved DMA1 RST DMA_1 Reset This bit resets the Receive DMA (Read) Channel 1 0 = Normal operation.
  • Page 42 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 23: I (ICR) 011A ABLE NTERRUPT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-3 Reserved Reserved INT_WC_RUR Interrupt Write-to-Clear or Reset-upon-Read Select This bit configures all Interrupt Status bits to be either Reset Upon...
  • Page 43 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 25: C (CIAGR) 011C ABLE USTOMER NSTALLATION LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:4] Reserved Reserved [3:2] CIAG CI Alarm Transmit (Only in ESF) These two bits are used to enable or disable AIS-CI or RAI-CI gen- eration in T1 ESF mode only.
  • Page 44 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 26: P (PRCR) 011D ABLE ERFORMANCE EPORT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION LBO_ADJ_ENB Transmit Line Build Out Auto Adjustment: This bit is used to enable or disable the transmit line build out auto adjustment feature.
  • Page 45 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 27: G (GCCR) 011E ABLE APPED LOCK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FrOutclk Framer Output Clock Reference This bit is used to enable or disable high-speed T1 rate on the T1OSCCLK and the E1OSCCLK output pins.
  • Page 46 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 28: T (TICR) 0120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSyncFrD Tx Synchronous fraction data interface This bit selects whether TxCHCLK or TxSERCLK will be used for fractional data input if fractional interface is enabled.
  • Page 47 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 28: T (TICR) 0120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxFr1544 Fractional/Signaling Interface Enabled This bit is used to enable or disable the transmit fractional data interface, sig- naling input, as well as the 32MHz transmit clock and the transmit overhead Signal output.
  • Page 48 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 28: T (TICR) 0120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxIMODE[1:0] Transmit Interface Mode selection This bit determines the transmit interface speed. The exact function of these two bits depends on whether Multiplexed mode is enabled or disabled.
  • Page 49 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 28: T (TICR) 0120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxIMODE[1:0] (Continued) 30: T ABLE RANSMIT NTERFACE PEED WHEN ULTIPLEXED ODE IS MUXEN = 1)
  • Page 50 BERT_Switch BERT Switch This bit enables or disables the BERT switch function within the XRT86VL30 device. By enabling the BERT switch function, BERT functionality will be switched between the receive and transmit framer. T1 Receive framer will generate the BERT pattern and insert it onto the receive...
  • Page 51 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 31: BERT C & S (BERTCSR0) 0121 ABLE ONTROL TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION UnFramedBERT Unframed BERT Pattern This bit enables or disables unframed BERT pattern generation (i.e.
  • Page 52 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 32: R (RICR) 0122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSyncFrD Receive Synchronous fraction data interface This bit selects whether RxCHCLK or RxSERCLK will be used for fractional data output if receive fractional interface is enabled.
  • Page 53 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 32: R (RICR) 0122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxFr1544 Receive Fractional/Signaling Interface Enabled This bit is used to enable or disable the receive fractional output interface, receive signaling output, the serial channel number output, as well as the 8kHz and the received recovered clock output.
  • Page 54 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 32: R (RICR) 0122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 RxIMODE[1:0] Receive Interface Mode Selection[1:0] This bit determines the receive backplane interface speed. The exact func- tion of these two bits depends on whether Receive Multiplexed mode is enabled or disabled.
  • Page 55 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 32: R (RICR) 0122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 RxIMODE[1:0] (Continued):( 34: R ABLE ECEIVE NTERFACE PEED WHEN ULTIPLEXED ODE IS MUXEN = 1)
  • Page 56 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 35: BERT C & S (BERTCSR1) 0123 ABLE ONTROL TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION PRBSTyp PRBS Pattern Type This bit selects the type of PRBS pattern that the T1 Transmit/ Receive framer will generate or detect.
  • Page 57 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 35: BERT C & S (BERTCSR1) 0123 ABLE ONTROL TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxBERTLock Lock Status This bit indicates whether or not the Receive or Transmit BERT lock has obtained.
  • Page 58 UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length. There are four lengths supported by the XRT86VL30 as presented in the table below: ECEIVE OOPBACK CTIVATION RXLBCALEN[1:0] ENGTH Selects 4-bit receive loopback code activa-...
  • Page 59 UNCTION EFAULT ESCRIPTION PERATION 3-2 TXLBCLEN[1:0] Transmit Loopback Code Length This bit determines transmit loopback code length. There are four lengths supported by the XRT86VL30 as presented in the table below RANSMIT OOPBACK ODE ACTIVATION TXLBCLEN[1:0] ENGTH Selects 4-bit transmit loopback code...
  • Page 60 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 37: T (TLCR) 0125 ABLE RANSMIT OOPBACK ODER EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 TXLBC[6:0] 1010101 Transmit Loopback Code These seven bits determine the transmit loopback code. The MSB of the transmit loopback code is loaded first for transmission.
  • Page 61 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 40: D (DDER) 0129 ABLE EFECT ETECTION NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION DEFDET For defect detection per ANSI T1.231-1997 and T1.403-1999, user should leave this bit set to ‘1’.
  • Page 62 Receive Loopback Code Activation Register if Receive activa- tion loopback code is enabled (Register address:0x0126). The XRT86VL30 will cancel the remote loopback upon detecting the loopback code deactivation code specified in the Receive Loopback Code Deactivation register if the Receive deactivation loopback code is enabled.
  • Page 63 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 42: R 1 (RLACR1) 012B ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.
  • Page 64 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 44: L 2 (LCCR2) 012D ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.
  • Page 65 Receive Loopback Code Activation Register if Receive activa- tion loopback code is enabled (Register address:0x0126). The XRT86VL30 will cancel the remote loopback upon detecting the loopback code deactivation code specified in the Receive Loopback Code Deactivation register if the Receive deactivation loopback code is enabled.
  • Page 66 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 45: R 2 (RLACR2) 012E ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.
  • Page 67 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 47: T SPRM NPRM C (TSPRMCR) 0142 ABLE RANSMIT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FC_Bit NPRM FC Bit This bit is used to set the value of the FC bit field within the NPRM report.
  • Page 68 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 48: D (DLCR2) 0143 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 Data Link SLC®96 DataLink Enable Enable This bit permits the user to configure the channel to support the transmission and reception of the “SLC-96 type”...
  • Page 69 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 48: D (DLCR2) 0143 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_IDLE Transmit Idle (Flag Sequence Byte) This bit configures the Transmit HDLC Controller Block #2 to uncon- ditionally transmit a repeating string of Flag Sequence octets (0X7E) in the data link channel to the Remote terminal.
  • Page 70 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 49: T (TDLBCR2) 0144 ABLE RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxHDLC2 BUFAvail/ Transmit HDLC2 Buffer Available/Buffer Select BUFSel This bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below.
  • Page 71 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 50: R (RDLBCR2) 0145 ABLE ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RBUFPTR Receive HDLC2 Buffer-Pointer This bit Identifies which Receive HDLC2 buffer contains the most recently received HDLC2 message.
  • Page 72 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 51: D (DLCR3) 0153 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 Data SLC®96 DataLink Enable Link Enable This bit permits the user to configure the channel to support the transmission and reception of the “SLC-96 type”...
  • Page 73 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 51: D (DLCR3) 0153 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_IDLE Transmit Idle (Flag Sequence Byte) This bit configures the Transmit HDLC Controller Block #3 to unconditionally transmit a repeating string of Flag Sequence octets (0X7E) in the data link channel to the Remote terminal.
  • Page 74 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 52: T (TDLBCR3) 0154 ABLE RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxHDLC3 BUFAvail/ Transmit HDLC3 Buffer Available/Buffer Select BUFSel This bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below.
  • Page 75 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 53: R (RDLBCR3) 0155 ABLE ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RBUFPTR Receive HDLC2 Buffer-Pointer This bit Identifies which Receive HDLC3 buffer contains the most recently received HDLC3 message.
  • Page 76 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 54: BERT C (BCR) 0163 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 Reserved Reserved 3-0 BERT[3:0] 0000 BERT Pattern Select 0010 =PRBS X20 + X3 + 1...
  • Page 77 T1 synchronization messages are sent through the FDL (Facility Data Link) bits by using a BOC (Bit Oriented Code) controller within the XRT86VL30 device. The most right bit position in the BOC code is sent first. The SSM message that are used in typical BITS applications are shown below. These messages are defined in specification ANSI T1.101-1999.
  • Page 78 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 56: SSM BOC C (BOCCR 0 0170 ABLE ONTROL EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 TxABORT RMF[1:0] RBOCE BOCR RBF[1:0] SBOC Auto Clear Auto Clear BIT 7 - Transmit Abort Sequence Enable By default, the transmitter will send an IDLE flag after the SSM message (unless continous is set).
  • Page 79 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 57: SSM R FDL R (RFDLR 0 0171 ABLE ECEIVE EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved RBOC[5:0] BITS [7:6] - Reserved BITS [5:0] - Receive BOC Message These bits contain the most recently received BOC message if the filter setting has been meet in bits[2:1] of register 0xn170h.
  • Page 80 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 58: SSM R FDL M (RFDLMR1 0 0172 ABLE ECEIVE ATCH EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved RFDLM1[5:0] BITS [7:6] - Reserved BITS [5:0] - Receive FDL Match 1 These bits can be used to set an expected value to be compared to the actual receive FDL message.
  • Page 81 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 61: SSM T FDL R (TFDLR 0 0175 ABLE RANSMIT EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved TBOC[5:0] BITS [7:6] - Reserved BITS [5:0] - Transmit BOC Message These bits are used to store the BOC message to be transmitted out the FDL bits.
  • Page 82 7-0 REVID[7:0] 00000001 REVID This register is used to identify the revision number of the XRT86VL30. The value of this register for the first revision is A - 0x01h. : The content of this register is subject to change when a newer...
  • Page 83 Register 0x0300 represents D/E time slot 0, and 0x0317 represents D/E time slot 23. 5 - 4 TxZERO[1:0] Selects Type of Zero Suppression These bits select the type of zero code suppression used by the XRT86VL30 device ZERO[1:0] YPE OF UPPRESSION ELECTED No zero code suppression is used AT&T bit 7 stuffing is used...
  • Page 84 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 65: T 0-23 (TCCR 0-23) 0300 0317 ABLE RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 TxCond(3:0) 0000 Transmit Channel Conditioning for Timeslot 0 to 23 These bits allow the user to substitute the input PCM data (Octets 0-23) with internally generated Conditioning Codes prior to transmission to the remote terminal equipment on a per-channel basis.
  • Page 85 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 66: T 0-23 (TUCR 0-23) 0320 0337 ABLE RANSMIT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TUCR[7:0] b00010111 Transmit Programmable User code. These eight bits allow users to program any code in this register to...
  • Page 86 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 67: T 0-23 (TSCR 0-23) 0340 0357 ABLE RANSMIT IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION A (x) See Note Transmit Signaling bit A This bit allows user to provide signaling Bit A (Octets 0-23) if...
  • Page 87 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 67: T 0-23 (TSCR 0-23) 0340 0357 ABLE RANSMIT IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSIGSRC[1] See Note Channel signaling control These bits determine the source for signaling information, see table...
  • Page 88 : Register 0x0360 represents D/E time slot 0, and 0x0377 represents D/E time slot 23. 5-4 RxZERO[1:0] Type of Zero Suppression These bits select the type of zero code suppression used by the XRT86VL30 device. YPE OF UPPRESSION ZERO[1:0] ELECTED No zero code suppression is used AT&T bit 7 stuffing is used...
  • Page 89 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 68: R 0-23 (RCCR 0-23) 0360 0377 ABLE ECEIVE HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 RxCOND[3:0] 0000 Receive Channel Conditioning for Timeslot 0 to 23 These bits allow the user to substitute the input line data (Octets 0-23) with internally generated Conditioning Codes prior to transmission to the back- plane interface on a per-channel basis.
  • Page 90 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 69: R 0-23 (RUCR 0-23) 0380 0397 ABLE ECEIVE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-0 RxUSER[7:0] 11111111 Receive Programmable User code. These eight bits allow users to program any code in this register to...
  • Page 91 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 70: R 0-23 (RSCR 0-23) 03A0 03B7 ABLE ECEIVE IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SIGC_ENB Signaling substitution enable This bit enables or disables signaling substitution on the receive side.
  • Page 92 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 70: R 0-23 (RSCR 0-23) 03A0 03B7 ABLE ECEIVE IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-2 RxSIGC[1:0]] Signaling conditioning [1:0] These bits allow user to select the format of signaling substitution on a per-channel basis, as presented in the table below.
  • Page 93 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 71: R 0-23 (RSSR 0-23) H 03C0 03D7 ABLE ECEIVE UBSTITUTION IGNALING EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 Reserved Reserved SIG16-A, 4-A, 2-A 16-code/4-code/2-code Signaling Bit A This bit provides the value of signaling bit A to substitute the receive signaling bit A when 16-code or 4-code or 2-code signaling substitu- tion is enabled.
  • Page 94 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 72: R 23 (RSAR 0-23) 0500 0517 ABLE ECEIVE IGNALING RRAY EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 Reserved Reserved These READ ONLY registers reflect the most recently received sig- naling value (A,B,C,D) associated with timeslot 0 to 31.
  • Page 95 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 73: LAPD B (LAPDBCR0) 0600 ABLE UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-0 LAPD Buffer 0 LAPD Buffer 0 (96-Bytes) Auto Incrementing This register is used to transmit and receive LAPD messages within buffer 0 of the HDLC controller.
  • Page 96 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 75: PMON R MSB (RLCVCU) 0900 ABLE ECEIVE IOLATION OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RLCVC[15] Performance Monitor “Receive Line Code Violation” 16-bit Counter - Upper Byte: RLCVC[14] These RESET-upon-READ bits, along with that within the PMON...
  • Page 97 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 77: PMON R MSB (RFAECU) H 0902 ABLE ECEIVE RAMING LIGNMENT RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RFAEC[15] Performance Monitor “Receive Framing Alignment Error 16-Bit counter” - Upper Byte: RFAEC[14] These RESET-upon-READ bits, along with that within the “PMON...
  • Page 98 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 79: PMON R (RSEFC) 0904 ABLE ECEIVE EVERELY RRORED RAME OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSEFC[7] Performance Monitor - Receive Severely Errored frame Counter (8-bit Counter) RSEFC[6] These Reset-Upon-Read bit fields reflect the cumulative number of...
  • Page 99 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 80: PMON R CRC-6 BIT E - MSB (RSBBECU) 0905 ABLE ECEIVE RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSBBEC[15] Performance Monitor “Receive Synchronization Bit Error 16-Bit Counter” - Upper Byte: RSBBEC[14] These RESET-upon-READ bits, along with that within the “PMON...
  • Page 100 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 82: PMON R (RSC) 0909 ABLE ECEIVE OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSC[7] Performance Monitor - Receive Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of...
  • Page 101 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 85: PMON LAPD1 F 1 (LFCSEC1) 090C ABLE RAME HECK EQUENCE RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FCSEC1[7] Performance Monitor - LAPD 1 Frame Check Sequence Error Counter (8-bit Counter)
  • Page 102 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 88: T (TSC) 090F ABLE RANSMIT OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSLIP[7] Performance Monitor - Transmit Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of...
  • Page 103 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 91: PMON LAPD2 F 2 (LFCSEC2) 091C ABLE RAME HECK EQUENCE RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FCSEC2[7] Performance Monitor - LAPD 2 Frame Check Sequence Error Counter (8-bit Counter)
  • Page 104 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 93: B (BISR) 0B00 ABLE LOCK NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved For E1 mode only LBCODE Loopback Code Block Interrupt Status This bit indicates whether or not the Loopback Code block has an interrupt request awaiting service.
  • Page 105 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 93: B (BISR) 0B00 ABLE LOCK NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLIP Slip Buffer Block Interrupt Status This bit indicates whether or not the Slip Buffer block has any out- standing interrupt request awaiting service.
  • Page 106 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 94: B (BIER) 0B01 ABLE LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved For E1 mode only LBCODE_ENB Loopback Code Block interrupt enable This bit permits the user to either enable or disable the Loopback Code Interrupt Block for interrupt generation.
  • Page 107 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 94: B (BIER) 0B01 ABLE LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLIP_ENB Slip Buffer Block Interrupt Enable This bit permits the user to either enable or disable the Slip Buffer Block for interrupt generation.
  • Page 108 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 95: A & E (AEISR) 0B02 ABLE LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Rx OOF Receive Out of Frame Defect State State This READ-ONLY bit indicates whether or not the Receive T1 Framer block is currently declaring the “Out of Frame”...
  • Page 109 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 95: A & E (AEISR) 0B02 ABLE LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Rx OOF RUR/ Change in Receive Out of Frame Defect Condition Interrupt Status.
  • Page 110 Line Code violation interrupt enable This bit permits the user to either enable or disable the “Line Code Viola- tion” interrupt within the XRT86VL30 device. If the user enables this inter- rupt, then the Receive T1 Framer block will generate an interrupt when Line Code Violation is detected.
  • Page 111 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 97: F (FISR) 0B04 ABLE RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 - Reserved (For E1 mode only) RUR/ Change in Signaling Bits Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Signaling Bits”...
  • Page 112 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 97: F (FISR) 0B04 ABLE RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RUR/ Frame Mimic Detection Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Frame Mimic Detection”...
  • Page 113 Change in Signaling Bits Interrupt Enable This bit permits the user to either enable or disable the “Change in Sig- naling Bits” Interrupt, within the XRT86VL30 device. If the user enables this interrupt, then the Receive T1 Framer block will generate an inter- rupt when it detects a change in the any four signaling bits (A,B,C,D) in any one of the 24 signaling channels.
  • Page 114 Framing Bit Error Interrupt Enable This bit permits the user to either enable or disable the “Framing Align- ment Bit Error Detection” Interrupt, within the XRT86VL30 device. If the user enables this interrupt, then the Receive T1 Framer block will gen- erate an interrupt when it detects one or more Framing Alignment Bit error within the incoming T1 data stream.
  • Page 115 This READ ONLY bit indicates the type of data link message received by Receive HDLC 1 Controller. Two types of data link mes- sages are supported within the XRT86VL30 device: Message Ori- ented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Indicates Bit-Oriented Signaling (BOS) type data link message is...
  • Page 116 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 99: D 1 (DLSR1) 0B06 ABLE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxEOT RUR/ Receive HDLC1 Controller End of Reception (RxEOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive HDLC1 Controller End of Reception (RxEOT) Interrupt has occurred since the last read of this register.
  • Page 117 Enable This bit enables or disables the “Receive HDLC1 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive HDLC1 Controller will generate an interrupt when it has started to receive a data link message.
  • Page 118 FCS Error Interrupt Enable This bit enables or disables the “Received FCS Error “Interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive HDLC1 Controller will generate an interrupt when it has detected the FCS error within the incoming data link message.
  • Page 119 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 101: S (SBISR) 0B08 ABLE UFFER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSB_FULL RUR/ Transmit Slip buffer Full Interrupt Status This Reset-Upon-Read bit indicates whether or not the Transmit Slip Buffer Full interrupt has occurred since the last read of this register.
  • Page 120 96 is in SYNC This READ ONLY bit field indicates whether or not frame synchroni- ® zation is achieved when the XRT86VL30 is configured in SLC framing mode. ® 0 = Indicates that frame synchronization is not achieved in SLC framing mode.
  • Page 121 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 101: S (SBISR) 0B08 ABLE UFFER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSB_EMPT RUR/ Receive Slip buffer Empty Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer Empty interrupt has occurred since the last read of this regis- ter.
  • Page 122 Transmit Slip Buffer Full Interrupt Enable This bit enables or disables the Transmit Slip Buffer Full interrupt within the XRT86VL30 device. Once this interrupt is enabled, the transmit Slip Buffer Full interrupt is declared when the transmit slip buffer is filled. If the transmit slip buffer is full and a WRITE opera- tion occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ‘1’.
  • Page 123 Receive Slip Buffer Full Interrupt Enable This bit enables or disables the Receive Slip Buffer Full interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive Slip Buffer Full interrupt is declared when the receive slip buffer is filled. If the Receive slip buffer is full and a WRITE opera- tion occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ‘1’.
  • Page 124 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 103: R (RLCISR) 0B0A ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...
  • Page 125 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 104: R (RLCIER) 0B0B ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...
  • Page 126 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 105: E (EXZSR) 0B0E ABLE XCESSIVE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 Reserved Reserved EXZ_STATUS RUR/ Change in Excessive Zero Condition Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Excessive Zero Condition”...
  • Page 127 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 107: SS7 S LAPD1 (SS7SR1) 0B10 ABLE TATUS EGISTER FOR DDRESS UNCTION EFAULT ESCRIPTION PERATION SS7_1_STATUS RUR/ SS7 Interrupt Status for LAPD Controller 1 This Reset-Upon-Read bit field indicates whether or not the “SS7”...
  • Page 128 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 109: R LOS/CRC I (RLCISR) 0B12 ABLE NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved RxLOSINT RUR/ Change in Receive LOS condition Interrupt Status This bit indicates whether or not the “Change in Receive LOS condi- tion”...
  • Page 129 This READ ONLY bit indicates the type of data link message received by Receive HDLC 2 Controller. Two types of data link mes- sages are supported within the XRT86VL30 device: Message Ori- ented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Indicates Bit-Oriented Signaling (BOS) type data link message is...
  • Page 130 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 111: D 2 (DLSR2) 0B16 ABLE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxEOT RUR/ Receive HDLC2 Controller End of Reception (RxEOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive HDLC2 Controller End of Reception (RxEOT) Interrupt has occurred since the last read of this register.
  • Page 131 Enable This bit enables or disables the “Receive HDLC2 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive HDLC2 Controller will generate an interrupt when it has started to receive a data link message.
  • Page 132 FCS Error Interrupt Enable This bit enables or disables the “Received FCS Error “Interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive HDLC2 Controller will generate an interrupt when it has detected the FCS error within the incoming data link message.
  • Page 133 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 113: SS7 S LAPD2 (SS7SR2) 0B18 ABLE TATUS EGISTER FOR DDRESS UNCTION EFAULT ESCRIPTION PERATION SS7_2_STATUS RUR/ SS7 Interrupt Status for LAPD Controller 2 This Reset-Upon-Read bit field indicates whether or not the “SS7”...
  • Page 134 This READ ONLY bit indicates the type of data link message received by Receive HDLC 3 Controller. Two types of data link messages are supported within the XRT86VL30 device: Message Oriented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Indicates Bit-Oriented Signaling (BOS) type data link message is...
  • Page 135 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 115: D 3 (DLSR3) 0B26 ABLE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxEOT RUR/ Receive HDLC3 Controller End of Reception (RxEOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive HDLC3 Controller End of Reception (RxEOT) Interrupt has occurred since the last read of this register.
  • Page 136 Enable This bit enables or disables the “Receive HDLC3 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive HDLC3 Controller will generate an interrupt when it has started to receive a data link message.
  • Page 137 FCS Error Interrupt Enable This bit enables or disables the “Received FCS Error “Interrupt within the XRT86VL30 device. Once this interrupt is enabled, the Receive HDLC3 Controller will generate an interrupt when it has detected the FCS error within the incoming data link message.
  • Page 138 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 117: SS7 S LAPD3 (SS7SR3) 0B28 ABLE TATUS EGISTER FOR DDRESS UNCTION EFAULT ESCRIPTION PERATION SS7_3_STATUS RUR/ SS7 Interrupt Status for LAPD Controller 3 This Reset-Upon-Read bit field indicates whether or not the “SS7”...
  • Page 139 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 119: C (CIASR) 0B40 ABLE USTOMER NSTALLATION LARM TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:6] Reserved Reserved RxAIS-CI_state Receive Alarm Indication Signal-Customer Installation (AIS-CI) State This READ ONLY bit field indicates whether or not the Receive T1 Framer is currently detecting the Alarm Indication Signal-Customer Installation (AIS- CI) condition.
  • Page 140 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 119: C (CIASR) 0B40 ABLE USTOMER NSTALLATION LARM TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxAIS-CI RUR/ Change in Receive AIS-CI Condition Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in AIS- CI Condition”...
  • Page 141 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 121: T1 BOC I (BOCISR 0 0B70 ABLE NTERRUPT TATUS EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RMTCH3 RMTCH2 BOCC RFDLAD RFDLF TFDLE RMTCH1 RBOC BIT 7 - Receive FDL Match 3 Event This bit is set when the receive FDL message is equal to the RFDL Match 3 message, and filter validation has occured.
  • Page 142 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 BIT 2 - TFDL Register Empty Event (Transmit End of Transfer) This bit is set when the TFDL register has been emptied according to amount of repetitions programmed into the TxBYTE count register 0xn178h.
  • Page 143 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 122: T1 BOC I (BOCIER 0 0B71 ABLE NTERRUPT NABLE EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RMTCH3 RMTCH2 BOCC RFDLAD RFDLF TFDLE RMTCH1 RBOC BIT 7 - Receive FDL Match 3 Event This bit is used to enable the RFDL Match 3 message Interrupt.
  • Page 144 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 123: T1 BOC U (BOCUISR 0 0B74 ABLE NSTABLE NTERRUPT TATUS EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved Unstable Reserved BIT 7 - Reserved BIT 6 - Unstable SSM Message Interrupt Status This bit will be set to ’1’...
  • Page 145 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 124: T1 BOC U (BOCUIER 0 0B75 ABLE NSTABLE NTERRUPT NABLE EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved Unstable Reserved BIT 7 - Reserved BIT 6 - Unstable SSM Message Interrupt Enable This bit is used to enable the Unstable SSM message Interrupt.
  • Page 146 Receiver ON: This bit permits the user to either turn on or turn off the Receive Sec- tion of XRT86VL30. If the user turns on the Receive Section, then XRT86VL30 will begin to receive the incoming data-stream via the RTIP and RRING input pins.
  • Page 147 8 Arbitrary Pulse Segments provided in the LIU registers (0x0F08-0x0F0F), where n is the channel number. The XRT86VL30 device supports both long haul and short haul applications which can also be selected using the EQC[4:0] bits. Table 126 .presents the corresponding Transmit Line Build Out and...
  • Page 148 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 126: E ABLE QUALIZER ONTROL AND RANSMIT UILD EQC[4:0] T1 M ECEIVE ENSITIVITY RANSMIT ABLE 0x00h T1 Long Haul/36dB 100Ω TP 0x01h T1 Long Haul/36dB -7.5dB 100Ω TP 0x02h...
  • Page 149 Receive Jitter Attenuator Enable This bit permits the user to enable or disable the Jitter Attenuator in the Receive Path within the XRT86VL30 device. 0 = Disables the Jitter Attenuator to operate in the Receive Path within the Receive T1 LIU Block.
  • Page 150 Transmit Jitter Attenuator Enable This bit permits the user to enable or disable the Jitter Attenuator in the Transmit Path within the XRT86VL30 device. 0 = Disables the Jitter Attenuator to operate in the Transmit Path within the Transmit T1 LIU Block.
  • Page 151 Loop-Up Code of “00001” to the line for the selected channel num- ber n. When Network Loop-Up code is being transmitted, the XRT86VL30 will ignore the “Automatic Loop-Code detection and Remote Loop- Back activation” (NLCDE1 =“1”, NLCDE0 =“1” of register 0x0F03) in order to avoid activating Remote Digital Loop-Back automatically when the remote terminal responds to the Loop-Back request.
  • Page 152 This bit permits the user to either turn on or turn off the Transmit Driver of XRT86VL30. If the user turns on the Transmit Driver, then XRT86VL30 will begin to transmit T1 data (on the line) via the TTIP and TRING output pins.
  • Page 153 When this mode is enabled, the state of the NLCD bit (bit 3 of regis- ter 0x0F05) is reset to “0” and the XRT86VL30 is configured to mon- itor the receive data for the Loop-Up code. If the “00001” pattern is detected for longer than 5 seconds, then the NLCD bit (bit 3 of regis- ter 0x0F05) is set “1”, and Remote Loop-Back is activated.
  • Page 154 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 129: LIU C 3 (LIUCCR3) 0F03 ABLE HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION INSBER_n Insert Bit Error: This bit is used to insert a single bit error on the transmitter of the T1 LIU Block.
  • Page 155 This bit permits the user to either enable or disable the “Change of Transmit DMO Condition” Interrupt. If the user enables this interrupt, then the XRT86VL30 device will generate an interrupt any time when either one of the following events occur.
  • Page 156 This bit permits the user to either enable or disable the “Change of the Receive LOS Defect Condition” Interrupt. If the user enables this inter- rupt, then the XRT86VL30 device will generate an interrupt any time when either one of the following events occur.
  • Page 157 Transmit Out- put Line signal. 0 = Indicates that the Transmit Section of XRT86VL30 is NOT cur- rently declaring the Transmit DMO Alarm condition. 1 = Indicates that the Transmit Section of XRT86VL30 is currently declaring the Transmit DMO Alarm condition.
  • Page 158 Automatic Loop-code detection mode (i.e., If NLCDE1 = “1” and NLCDE0 =”1”), the state of the NLCD sta- tus bit is reset to “0” and the XRT86VL30 is programmed to monitor the receive input data for the Loop-Up code. This bit is set to a “1” to indicate that the Network Loop Code is detected for more than 5 seconds.
  • Page 159 This READ-ONLY bit indicates whether or not the Receive LIU Block is currently declaring the QRSS Pattern LOCK status. 0 = Indicates that the XRT86VL30 is NOT currently declaring the QRSS Pattern LOCK. 1 = Indicates that the XRT86VL30 is currently declaring the QRSS Pattern LOCK.
  • Page 160 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 132: LIU C (LIUCCISR) 0F06 ABLE HANNEL ONTROL NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved DMOIS_n RUR/ Change of Transmit DMO (Drive Monitor Output) Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the “Change of...
  • Page 161 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 132: LIU C (LIUCCISR) 0F06 ABLE HANNEL ONTROL NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RLOSIS_n RUR/ Change of Receive LOS (Loss of Signal) Defect Condition Inter- rupt Status: This RESET-upon-READ bit indicates whether or not the “Change of...
  • Page 162 Arbitrary Transmit Pulse Shape, Segment 1: These seven bits form the first of the eight segments of the transmit shape pulse when the XRT86VL30 is configured in “Arbitrary Mode”. These seven bits represent the amplitude of the nth channel's arbi- trary pulse in signed magnitude format with Bit 6 as the sign bit and Bit 0 as the least significant bit (LSB).
  • Page 163 Arbitrary Transmit Pulse Shape, Segment 4 These seven bits form the forth of the eight segments of the transmit shape pulse when the XRT86VL30 is configured in “Arbitrary Mode”. These seven bits represent the amplitude of the nth channel's arbi- trary pulse in signed magnitude format with Bit 6 as the sign bit and Bit 0 as the least significant bit (LSB).
  • Page 164 Arbitrary Transmit Pulse Shape, Segment 7 These seven bits form the seventh of the eight segments of the transmit shape pulse when the XRT86VL30 is configured in “Arbi- trary Mode”. These seven bits represent the amplitude of the nth channel's arbi- trary pulse in signed magnitude format with Bit 6 as the sign bit and Bit 0 as the least significant bit (LSB).
  • Page 165 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 142: LIU G 0 (LIUGCR0) 0FE0 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Single Rail mode This bit must set to "1" for Single Rail mode to use LIU diagnotic fea- tures.
  • Page 166 Software Reset µ P Registers: SRESET This bit allows users to reset the XRT86VL30 device. Writing a “1” to this bit and keeping it at ’1’ for longer than 10µs initiates a device reset through the microprocessor interface. Once the XRT86VL30 is reset, all internal circuits are placed in the reset state except the microprocessor register bits.
  • Page 167 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0...
  • Page 168 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 143: LIU G 1 (LIUGCR1) 0FE1 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSYNC(Sect 13) G.703 Section 13 Transmit Pulse When this bit is set to ’1’, the LIU transmitter will send a T1 syn- chrnonous waveform as described in Section 13 of ITU-T G.703,...
  • Page 169 This bit allows users to tristate the output pins of all channels for in- circuit testing purposes. When In-Circuit-Testing is enabled, all output pins of the XRT86VL30 are “Tri-stated”. When In-Circuit-Testing is disabled, all output pins will resume to normal condition. 0 = Disables the In-Circuit-Testing Feature.
  • Page 170 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 145: LIU G 3 (LIUGCR3) 0FE4 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved These Bits are Not Used. MCLKn[1:0] Master T1 Output Clock Reference [1:0] These two bits allow users to select the programmable output clock rates for the MCLKnOUT pin, according to the table below.
  • Page 171 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 146: LIU G 4 (LIUGCR4) 0FE9 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved CLKSEL[3:0] 0001 Clock Select Input [3:0] These four bits allow users to select the programmable input clock rates for the MCLKIN input pin, according to the table below.
  • Page 172 Global Channel 0 Interrupt Status Indicator This Reset-Upon-Read bit field indicates whether or not an interrupt has occurred on Channel 0 within the XRT86VL30 device since the last read of this register. 0 = Indicates that No interrupt has occurred on Channel 0 within the XRT86VL30 device since the last read of this register.
  • Page 173 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 ORDERING INFORMATION RODUCT UMBER ACKAGE PERATING EMPERATURE ANGE ° ° XRT86VL30IV 128 PIn LQFP (14x20x1.4mm) C to +85 ° ° XRT86VL30IV80 80 Pin LQFP (12x12x1.4mm) C to +85 PACKAGE DIMENSIONS FOR 128 LQFP...
  • Page 174 XRT86VL30 SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.0 PACKAGE DIMENSIONS FOR 80 LQFP 80 LEAD LOW-PROFILE QUAD FLAT PACK (12 x 12 X 1.4 mm LQFP) Rev. 1.00 Note: The control dimension is in the millimeter column...
  • Page 175 Initial release of the XRT86VL30 datasheet. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement.

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