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IDT VersaClock 6E Series Register Descriptions And Programming Manual

Programmable clock generator
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Register Descriptions

The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the
VersaClock 6E family of clock generators.
Table 1. VersaClock 6E Family Products
Product
5P49V6965
5P49V6967
5P49V6968
5P49V6975
For details of product operation, refer to the product datasheet.

VersaClock 6E Family Register Set

The device contains volatile (RAM) 8-bit registers and non-volatile 8-bit registers
Programmable (OTP), and bit values can only be changed from 1 (unburned state) to 0.
The OTP registers include factory trim data and four user configuration tables
format or methods for programming factory trim data, which is programmed by the factory before shipment.
Each configuration table contains all the information to set up the device's output frequencies. When these configuration tables are
programmed, the device will automatically load the RAM registers with the desired configuration on power-up. The device initializes in
2
either I
C mode or selection-pin mode, depending on the state of the OUT0/SELB_I2C pin on power-up, and remains in the selected
mode until power is toggled
selection-pin mode, the SEL0 and SEL1 inputs are decoded to select one of the four configuration tables CFG0-CFG3.
The RAM registers
(Table
4) include Status registers for read-back of the device's operating conditions in I
Figure 1. Register Maps
©2018 Integrated Device Technology, Inc.
VersaClock
Table 1
showcases the array of products under the VersaClock 6E family.
5-Output VersaClock 6E
8-Output VersaClock 6E with 4 LP-HCSL Outputs
12-Output VersaClock 6E with 8 LP-HCSL Outputs
5-Output VersaClock 6E with Internal Crystal
(Table
2). When powered up in I²C mode, the first configuration table, CFG0, is loaded. When powered up in
®
6E Family Register Descriptions
Description
(Figure
1). The non-volatile registers are One-Time
(Figure
1,
Table
1
and Programming Guide
Package
3). This document does not describe the
2
C mode.
24 pins
40 pins
48 pins
24 pins
August 30, 2018

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  • Page 1: Register Descriptions

    ® VersaClock 6E Family Register Descriptions and Programming Guide Register Descriptions The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the VersaClock 6E family of clock generators. Table 1 showcases the array of products under the VersaClock 6E family. Table 1.

  • Page 2: Table Of Contents

    ® VersaClock 6E Family Register Descriptions and Programming Guide Contents Register Descriptions ....................1 VersaClock 6E Family Register Set .

  • Page 3: User Configuration Table Selection

    ® VersaClock 6E Family Register Descriptions and Programming Guide User Configuration Table Selection At power-up, the voltage at OUT0_SEL_I2CB pin 24 is latched by the part and used to select the state of SEL0/SCL pin 9 and SEL1/SDA pin 8 (Table If a weak pull-up (10kΩ) is placed on OUT0_SEL_I2CB, the SEL0/SCL and SEL1/SDA pins will be configured as hardware select inputs, SEL0 and SEL1.

  • Page 4: Versaclock 6E Family Power-Up Behavior

    OTP user configuration tables have been programmed. • Factory programmed product is typically shipped in this condition. Device has factory trim performed and with required customization written into OTP memory. IDT programs user customization at factory test. Please visit our website for device customization request.

  • Page 5: Otp Programming

    ® VersaClock 6E Family Register Descriptions and Programming Guide OTP Programming The steps for OTP programming are given in Table 5. The procedure is to write the desired default data to the appropriate RAM registers, and then to instruct the part to burn a desired register address range into OTP. The RAM registers have an 8-bit register address (0x00 to 0x9F), while the user OTP registers have a 9-bit address (0x000 to 0x177).

  • Page 6: In-System Versaclock 6E Otp Non-Volatile Programming Via I2C

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 6. OTP Addressing For Programming User Start Enable User End User End Burned Register Read Register Registers Address[8:0] Sub-block's Address[8:0] Address[8:0] Register Start Address Start Address Burned To Part-Select Test Mode Part-Select Bit Part-Select 0x77...

  • Page 7: Otp Control Register

    ® VersaClock 6E Family Register Descriptions and Programming Guide OTP Control Register The I C slave address can be changed from the default 0xD4 to 0xD0 by programming the I2C_ADDR bit D0. Note that the I C address change occurs on the I C ACK of the write transaction.
  • Page 8 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 9. RAM0 – 0x02: Factory Reserved Bits - ADC Gain Setting Bits Default Value Name Function ADC gain[7:0] ADC gain setting - Factory reserved bits Table 10. RAM0 – 0x03: Factory Reserved Bits - ADC Gain Setting Bits Default Value Name...
  • Page 9 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 12. RAM0 – 0x05: Factory reserved bits - ADC OFFSET Bits Default Value Name Function ADC offset[15:8] ADC offset - Factory reserved bits Table 13. RAM0 – 0x06: Factory Reserved Bits Bits Default Value Name...
  • Page 10 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 15. RAM0 – 0x08: Factory Reserved Bits Bits Default Value Name Function GAIN<7:0> Unused Factory reserved bits Table 16. RAM0 – 0x09: Factory Reserved Bits Bits Default Value Name Function test[3:0] Factory reserved bits NP[3:0]...
  • Page 11 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 18. RAM0 – 0x0B: Factory Reserved Bits Bits Default Value Name Function bandgap_trim_up [5:0] bandgap voltage trim, one step is 1.2mV higher than current. unused bit unused bit Table 19. RAM0 – 0x0C: Factory Reserved Bits Bits Default Value Name...

  • Page 12: Configuration Registers

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 21. RAM0 – 0x0E: Factory Reserved Bits Bits Default Value Name Function clk3_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level. clk4_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level. CLK4_amp[0] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.
  • Page 13 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3 Summary (Cont.) Register Address Function CFG0 CFG1 CFG2 CFG3 Factory Reserved Register 0x14 0x014 0x06E 0x0C8 0x122 Reference Divider Register 0x15 0x015 0x06F...
  • Page 14 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3 Summary (Cont.) Register Address Function CFG0 CFG1 CFG2 CFG3 Output Divider 2 Step Spread Configuration Register 0x36 0x036 0x090 0x0EA 0x144...

  • Page 15: Configuration Register Detail And Functionality Description

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3 Summary (Cont.) Register Address Function CFG0 CFG1 CFG2 CFG3 Output Divider 4 Step Spread Configuration Register 0x58 0x058 0x0B2 0x10C 0x166...

  • Page 16: Setting Up A Low-Power Shutdown Mode Through I2C

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 24. Shutdown Truth Table SH bit SP bit OSn bit OEn bit SD/OE bit SD/OE pin OUTn Output Active Output Active Output Active Output Active Output Driven Logic “1” (High/Low) Output Driven Logic “1”...
  • Page 17 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 25. RAM1 – 0x10: Primary Source and Shutdown Register (Cont.) Bits Default Value Name Function Enable path from reference clock to OUT1. Set to 1 when OUT1 is a copy of the en_refmode reference clock (= OUT0).

  • Page 18: Crystal Load Capacitor Registers

    ® VersaClock 6E Family Register Descriptions and Programming Guide Crystal Load Capacitor Registers Registers 0x12 and 0x13 are Crystal X1 and X2 Load capacitor registers respectively that are used to add load capacitance to X1 and X2 respectively. In X1 Switch mode is provided with different mode selection options and in X2 polarity selection of clock can be made whose values are given in the table.

  • Page 19: Pll Pre-Divider Options

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 29. RAM1 – 0x13: Factory Reserved Bits Bits Default Value Name Function Add 6.92pF load capacitance to X2. Add 3.46pF load capacitance to X2. Add 1.73pF load capacitance to X2. xtal_load_cap_x2[5:0] Add 0.86pF load capacitance to X2.
  • Page 20 ® VersaClock 6E Family Register Descriptions and Programming Guide Figure 3. PLL Pre-Divider Options If pre-divider is selected by selecting bypass_ prediv = 0 (Table 31) then user can select divider by 2 or divider values from 3 to 127. Table 31.

  • Page 21: Pll Fractional Feedback Divider And Loop Filter

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 33. RAM1 – 0x11: VCO Band and Factory Reserved Bits Bits Default Value Name Function unused Unused Factory reserved bit. unused Unused Factory reserved bit. test_mode_vco_band “test_mode_vco_band” is 1 enables the VCO test mode. When bit D5 is 1, it forces the VCO to use the VCO band value in bits D0–4 and ignore vco_band[4:0] the VCO band (auto) calibration.
  • Page 22 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 35. RAM1 – 0x18: Feedback Integer Divider Bits Bits Default Value Name Function FB_intdiv[3:0] The Feedback Integer Divider Register has 12 bits spread on 2 registers 0x17 and 0x18. sdm_order_cfg[1] Factory Reserved bits.
  • Page 23 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 38. RAM1 – 0x1B: Feedback Fractional Divider Registers Bits Default Value Name Function The Feedback fractional divider has 24 bits divided amongst 3 registers (0x19, 0x1A and FB_frcdiv[7:0 0x1B). Table 39. RAM1 – 0x1C: Factory Reserved Bits Bits Default Value Name...
  • Page 24 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 40. RAM1 – 0x1D: Factory Reserved Bits Bits Default Value Name Function Charge-pump current control–Factory reserved bits. cfg_cp[3:0] 30uA step from 0 to 450uA. en_vco Enable or disable the VCO block.VCO needs to be enabled by default. Bypass global reset.

  • Page 25: Pll Loop Filter Settings

    ® VersaClock 6E Family Register Descriptions and Programming Guide PLL Loop Filter Settings Figure 4 below shows the Loop Filter components that are programmable via the RC control registers. Figure 4. PLL Loop Filter Components where Rz is programmable with register 0x1E. Cz is fixed and not programmable.

  • Page 26: Fractional Output Dividers And Spread Spectrum

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 42. RAM1 – 0x1F: RC Control Register Bits Default Value Name Function p3byp Enable or disable bypass 3rd pole filter 3rd pole RC configuration. Following values are programmable with bits D1 through D6: D3D2D1 = 001 →...
  • Page 27 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 43. Spread Spectrum Variables in FODx RAM Register Register Name Function (see Table Length Note If ODx_ssce = 0, contents of ODx_period and ODx_ssce Spread spectrum control enable. 0x25,0x35,0x45,0x55 ODx_step are Don't Care. Integer portion of the FODx 0x2D, 0x2E,0x3D,0x3E, ODx_intdiv...
  • Page 28 ® VersaClock 6E Family Register Descriptions and Programming Guide Figure 5. Spread Step and Period As normally defined, ODx_period (dec) would be 1/ F SS, but the modulation period is defined instead as ½*1/ FSS for the most direct calculation of ODx_step as will be seen below in the following Equations. An added benefit is that the up ramp and the down ramp are guaranteed to be symmetric.

  • Page 29: Example Of Fod Calculation For Ssce = 1

    ® VersaClock 6E Family Register Descriptions and Programming Guide Example of FOD calculation for SSCE = 1 Out1 of clock1 = 99MHz, spread enabled with total spread 0.5% and SS 31.5KHz. Feedback divider = 112.4, and VCO = 2810MHz. Let's calculate the FOD 1 value according to the equations above. /2 = 2810/2 = 1405, and FOUT = 99MHz (given).
  • Page 30 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 46. FOD1 Register Table Register Offsets Output (MHz) 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2C 0x2E 0x2F 97.1455 98.147 99.1485 100.15 101.1515 102.153 103.1545 Figure 6. Output Divider Control Settings Block Diagram en_refmode XIN/REF OUT0_SEL_I2CB...

  • Page 31: Output Divider Control Settings (Table 47 Through Table 50)

    ® VersaClock 6E Family Register Descriptions and Programming Guide Output Divider Control Settings (Table 47 through Table These bits are for Output divider's control register settings and are reserved in general. The reset bit for the FOD is active low. The combination of en_fod (fractional output divider enable bit), sel_ext (the output from previous channel FOD) and selb_norm (the output from current FOD), will set the divider mode.
  • Page 32 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 49. RAM4 – 0x41: Output Divider 3 Control Register Settings Bits Default Value Name Function i2c_resetb3 Reset Fractional Output Divider 3 (FOD3) circuit when set to 0. en_pi_out_cap<2:0> Factory reserved /unused bits. selb_norm3 0000: FOD3 and OUT3 are not used.
  • Page 33 ® VersaClock 6E Family Register Descriptions and Programming Guide Output Divider Integer Settings (Table 51 through Table Output divider's integer part consists of 12 bits spread on 2 consecutive registers. The 4 dividers are assigned to respectively to each output 1, 2, 3, 4. Table 51.
  • Page 34 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 54. RAM3 – 0x3E: Output Divider 2 Integer Part Bits Default Value Name Function OD2_intdiv[3:0] Output divider 2 integer part has 12 bit spread over 2 registers x3D and x3E. unused bits Unused Factory reserved bit.

  • Page 35: Output Divider Fractional And Spread Settings (Table 59 Through Table 94)

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 57. RAM5 – 0x5D: Output Divider 4 Integer Part Bits Default Value Name Function OD4_intdiv[11:4] Output divider 4 integer part has 12 bit spread over 2 registers x5D and x5E. Table 58.
  • Page 36 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 59. RAM2 – 0x22: Output Divider 1 Fractional Settings Bits Default Value Name Function OD1_offset[29:22] 30 bits to configure the fraction value of FOD1 in register address. x22, x23, x24 and x25. Table 60.
  • Page 37 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 62. RAM2 – 0x25: Output Divider 1 Fractional Settings Bits Default Value Name Function OD1_offset[5:0] 30 bits to configure the fraction value of FOD1 in register address x22, x23, x24 and x25. OD1_ssce Enable spread spectrum with center spread offset.
  • Page 38 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 65. RAM2 – 0x28: Output Divider 1 Step Spread Configuration Register Bits Default Value Name Function OD1_step[23:16] 24 bits used for modulation step size in register x26 x27 and x28. Table 66.
  • Page 39 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 68. RAM3 – 0x32: Output Divider 2 Fractional Settings Bits Default Value Name Function OD2_offset[29:6] 30 bits to configure the fraction value of FOD2 in register address x32, x33, x34 and x35. Table 69.
  • Page 40 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 71. RAM3 – 0x35: Output Divider 2 Fractional Settings Bits Default Value Name Function OD2_offset[5:0] 30 bits to configure the fraction value of FOD2 in register address x32, x33, x34 and x35. OD2_ssce Enable spread spectrum with center spread offset.
  • Page 41 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 74. RAM3 – 0x38: Output Divider 2 Step Spread Configuration Register Bits Default Value Name Function OD2_step[23:16] 24 bits used for modulation step size in register x36 x37 and x38. Table 75.
  • Page 42 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 77. RAM4 – 0x42: Output Divider 3 Fractional Settings Bits Default Value Name Function OD3_offset[29:6] 30 bits to configure the fraction value of FOD3 in register address x42, x43, x44 and x45. Table 78.
  • Page 43 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 80. RAM4 – 0x45: Output Divider 3 Fractional Settings Bits Default Value Name Function OD3_offset[5:0] 30 bits to configure the fraction value of FOD3 in register address x42, x43, x44 and x45. OD3_ssce Enable spread spectrum with center spread offset.
  • Page 44 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 83. RAM4 – 0x48: Output Divider 3 Step Spread Configuration Register Bits Default Value Name Function OD3_step[23:16] 24 bits used for modulation step size in register x46 x47 and x48. Table 84.
  • Page 45 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 86. RAM5 – 0x52: Output Divider 4 Fractional Settings Bits Default Value Name Function 30 bits to configure the fraction value of FOD4 in register addr. OD4_offset[29:6] x52, x53, x54 and x55 Table 87.
  • Page 46 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 89. RAM5 – 0x55: Output Divider 4 Fractional Settings Bits Default Value Name Function OD4_offset[5:0] 30 bits to configure the fraction value of FOD4 in register address x52, x53, x54 and x55. OD1_ssce Enable spread spectrum with center spread offset.
  • Page 47 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 92. RAM5 – 0x58: Output Divider 4 Step Spread Configuration Register Bits Default Value Name Function OD4_step[23:16] 24 bits used for modulation step size in register x56 x57 and x58. Table 93.

  • Page 48: Skew

    ® VersaClock 6E Family Register Descriptions and Programming Guide Skew Skew is not implemented with a parallel load of the count of the output divider as is commonly done with non-fractional divides. Instead skew is accomplished by increasing the value of the fractional output divider for only the very first clock cycle. The divide is increased by the number of VCO cycles required to delay the completion of the first output clock cycle by the desired skew.

  • Page 49: Output Divider Skew Integer And Fractional Part Registers Settings (Table 95 Through Table 107)

    ® VersaClock 6E Family Register Descriptions and Programming Guide To apply the 1.3ns skew on OUT1, write the following values: Addr – Byte 0x2B – 00 0x2C – 10 0x2F – 74 After writing these values all counters need to be restarted to insert the 1.3ns delay in OUT1 versus the other outputs. The restarting can be done by toggling the I C global reset in bit 5 of register 0x76.
  • Page 50 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 96. RAM2 – 0x2C: Output Divider 1 Skew Integer Part Bits Default Value Name Function OD1_intskew[3:0] 12 bits are used to set Output Divider 1 skew integer part in register x2B and x2C. unused bits Unused Factory reserved bit.

  • Page 51: Output Divider Integer Settings (Table 51 Through Table 58)

    ® VersaClock 6E Family Register Descriptions and Programming Guide Table 99. RAM3 – 0x3C: Output Divider 2 Skew Bits Default Value Name Function OD2_intskew[3:0] 12 bits are used to set Output Divider2 skew integer part in register x3B and x3C. unused bits Unused Factory reserved bit.
  • Page 52 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 102. RAM4 – 0x4C: Output Divider 3 Skew Bits Default Value Name Function OD3_intskew[3:0] 12 bits are used to set Output Divider3 skew integer part in register x4B and x4C. unused bits Unused Factory reserved bit.
  • Page 53 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 105. RAM5 – 0x5B: Output Divider 4 Skew Integer Part Bits Default Value Name Function OD4_intskew[11:4] 12 bits are used to set Output Divider4 skew integer part in register x5B and x5C. Table 106.

  • Page 54: Clock Output Configurations Registers

    ® VersaClock 6E Family Register Descriptions and Programming Guide Clock Output Configurations Registers In Clock Output Configuration registers described in the tables below, the CLKx_pwr_sel bits must be configured to match the clock outputs' supply voltages applied externally. The bits don't adjust the clock output signal swings. CMOSX2 provides two phase-coherent single ended CMOS outputs while CMOSD provides 2 signals out of phase by 180degree.
  • Page 55 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 110. RAM6 – 0x62: Clock2 Output Bits Default Value Name Function CLK2_cfg[2] These bits give us the output type configuration mode. For D7, D6, D5 respectively: CLK2_cfg[1] (D7, D6, D5) = 000: low-voltage positive/pseudo emitter-coupled logic (LVPECL); (D7, D6, D5) = 001: CMOS;...
  • Page 56 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 112. RAM6 – 0x64: Clock3 Output Bits Default Value Name Function CLK3_cfg[2] These bits give us the output type configuration mode. For D7, D6, D5 respectively: CLK3_cfg[1] (D7, D6, D5) = 000: low-voltage positive/pseudo emitter-coupled logic (LVPECL); (D7, D6, D5) = 001: CMOS;...
  • Page 57 ® VersaClock 6E Family Register Descriptions and Programming Guide Table 114. RAM6 – 0x66: Clock4 Output Bits Default Value Name Function CLK4_cfg[2] These bits give us the output type configuration mode. For D7,D6,D5 respectively: CLK4_cfg[1] (D7,D6,D5) = 000: low-voltage positive/pseudo emitter-coupled logic (LVPECL); (D7,D6,D5) = 001: CMOS;...

  • Page 58: Revision History

    IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users.

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