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3.Block diagram
XIN
XOUT
FMIN
AMIN
SNS
SNSFF
VDD
VSS
V-DET
HCTR
1/2
LCTR
HOLD
TEST1
TEST2
PA0
PA1
BUS
PA2
DRIV.
PA3
PB0
LATCH
PB1
BUS
PB2
DRIV.
BP3
PC0
LATCH
PC1
BUS
PC2
DRIV.
PC3
PD0
LATCH
PD1
BUS
PD2
DRIV.
PD3
PE0
SCK2/PE1
LATCH
BUS
PO2/PE2
DRIV.
SI2/PE3
PF0
SCK1/PF1
LATCH
BUS
SO1/PF2
DRIV.
SI1/PF3
SIO
PF0
SCK1/PF1
LATCH
BUS
SO1/PF2
DRIV.
SI1/PF3
DIVIDER
REFERENCE DIVIDER
1/16, 1/17
PROGRAMMABLE DIVIDER
1/114, 1/124
LATCH
UNIVERSAL
COUNTER
(20bits)
RAM
512 4bits
ROM
12K 16bits
ADDRESS DECODER
PROGRAM COUNTER
STACK
ALU
SELECTOR
PHASE
DETECTOR
UNLOCK
F/F
PHASE
DETECTOR
ADDRESS
DECODER
BEEP
BUS
DRIVER
INSTRU-
CTION
DECODER
JUDGE
ADC
MPX
KS-FX201
LC72362N-9920
E01
E02
SUBPD
SUB
C.P.
EO3
PQ0
LATCH
PP3
LATCH
PP2
BUS
PP1
DRIV.
PP0
PO3
LATCH
PO2
BUS
PO1
DRIV.
PO0
PN3
LATCH
PN2
BUS
PN1
DRIV.
MPX
PN0/BEEP
PM3
LATCH
PM2
BUS
PM1
DRIV.
PM0
PL3
LATCH
PL2
BUS
PL1
DRIV.
PL0
PK3
LATCH
PK2
BUS
PK1/INT1
DRIV.
PK0/INT0
INTERRUPT
PJ3
LATCH
PJ2
BUS
PJ1
DRIV.
PJ0
PI1/ADI5
BUS
DRIV.
PI0/ADI4
PH3/ADI3
PH2/ADI2
BUS
DRIV.
PH1/ADI1
PH0/ADI0
1-19
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