Schematic Diagrams - Yamaha YSP-900 Service Manual

A B C

SCHEMATIC DIAGRAMS

DSP 1/3
1
2
0.3
0
5.0
0
3.4
3.2
DIR
3
3.4
0
4
5
0.1
1.4
0
3.4
3.4
3.4
0
1.4
0.1
1.4
0
0.1
0.1
6
1.7
1.4
0
1.7
3.4
0
1.4
0
3.1
3.3
3.3
0
1.4
2.6
7
0
1.4
3.4
3.4
3.4
0
1.4
3.4
0
0
1.4
1.4
0
8
9
10
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
D E F
3.4
0
0
0
0
3.4
1.6
1.6
A-2
1.6 F.F
3.4
0
0
3.3
3.3
2.6
2.6
3.4
0
3.4
0
DSP1
No replacement part available.
サービス部品供給なし
1.4
IC7: SN74LVC74APWR
Dual positive-edge-triggered D-type flip flops
G H
3.3
0
3.2
3.2
1.2
1.2
3.3 0
4.8
1.7 1.7
1.7 1.7
0 0
2.5 0
2.5 5.0
2.5 2.5
3.4
1.7
0
1.7
1.2
3.3
1.3
1.4
0
3.3
0.7
1.3
0
0
0
3.4
1.7
1.7
3.4
0
1.4
3.2
3.2
3.2
3.3
3.2
3.2
3.4
0
1.4
3.2
3.2
3.2
5.2
3.4 0
3.2 3.2
3.2
3.2 3.2 3.3
3.4 0 0
1.4 3.2 3.2
0
3.3 3.2
3.4 3.2 3.4
3.2 3.2 3.4
3.2 3.2 3.2
3.2 0 0
3.2 3.2 3.2
3.2 3.2
3.2 3.3 3.4
3.2
3.4
0 3.3 3.2
1.4 3.3 1.7
3.3 3.3
3.3
0.3 0
0 0
0 2.9
0 2.6
3.3 1.7
3.3 2.7
0
3.4
DRAM
PRE
C
CLK C
C 1CLR
Q
1D
TG
1CLK
C C C
1PRE
C
1Q
D TG TG TG 1Q
GND
Q
C C C
CLR
I J K
IC1-3: PQ1CZ41H2Z
Chopper regulators
V
IN
1
Voltage ON/OFF
regulator circuit
PWM COMP.
Q
Overcurrent
R
detection F/F
circuit
S
ERROR AMP.
V
Overheat
detection
circuit
3
COM
IC4: LC89057W-VF4D-E
Digital audio interface transceiver
EMPHA/UO AUDIO/VO INT CL
32 33 35 48
RXOUT 1 Microcontroller
Cbit, Ubit
I/F
RX0 2
RX1 3
RX2 4
Demodulation
Input
Data
RX3 5 &
Selector
Selector
Lock detect
RX4 8
RX5/VI
9
RX6/UI 10
LPF PLL
13
Clock
TMCK/PIO0 44
Selector
TBCK/PIO1 45 Modulation
1/N
&
TLRCK/PIO2 46
Parallel Port
TDATA/PIO3 47
TXO/PIOEN 48
29 28 27 34
XIN XOUT XMCK CKST
IC5: D60YA003BPYP225
Decoder
Digital Signal Processors
EMIF32 L2 Cache/
L1P Cache
Memory
4 Banks Direct Mapped
McASP1
64K Bytes 4K Bytes Total
Total
McASP0
(4-Way)
McBSP1
Instruction Fetch
McBSP0 Instruction Dispatch
L2 Instruction Decode
I2C1 Enhanced
Memory
DMA Data Path A
Controller
I2C0 DA610:
(16 channel) A Register File
192K Bytes
Timer 1
DA601:
64K Bytes .L1t .S1t .M1t .D1
Timer 0
GP1
L1D Cache
2-Way Set
GP0
R2 ROM
Associative
512K
4K Bytes Total
HPI16 Bytes
Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
IC11: S29AL004D70TFI020
4M-bit COMS 3.0 volt-only boot sector flash memory
V
CC
V
SS
RESET#
0 0
0 3.4
0 0
WE#
0 3.2
BYTE#
0.3 3.2
0 3.3
0 3.2
0 3.2
3.2
3.2
3.3 3.2 CE#
0 3.4
OE#
3.4
3.3
POINT A-2 pin 29 of IC4
3.2
0
3.2
3.2
0
2.9 3.2
2.6 3.2
1.7 3.2
2.7 3.3
3.3 0
3.3 3.3
0 0
A0–A17
FLASH
DSP IC10: WM8738
24bit stereo ADC
6 4 11
9
AVDD
CONTROL
INTERFACE
5
CAP
AGND 10
VCC
1 14 RIN 7 ADC 2 SDATO
2 13 2CLR
LRCLK
12
3 12 2D DIGITAL AUDIO
FILTERS INTERFACE
4 11 2CLK 3 BCLK
5 10 2PRE
13 MCLK
LIN 8 ADC
6 9 2Q
7 8
2Q
1 14
L M N
YSP-900
IC9: W9816G6CH
512K x 2 banks x 16 bits SDRAM
V
OUT
2 CLK 35
CLOCK
BUFFER
CKE 34
ON/OFF COLUMN DECODER
CS 18 CONTROL
5 SIGNAL
control R
RAS 17
GENERATOR O
COMMAND
W
DECODER
CAS 16
D CELL ARRAY
2 DQ0
E
WE 15 BANK #0
C
3 DQ1
O
D
5 DQ2
E
R
O A10 20
adj 6 DQ3
4
SENSE AMPLIFIER
8 DQ4
ref 9 DQ5
MODE
A0 21 11 DQ6
〜 REGISTER
ADDRESS 12 DQ7
A3 24
REFRESH DQ
BUFFER
COUNTER BUFFER 39 DQ8
A4 27
〜
40 DQ9
A9 32
42 DQ10
BA 19
43 DQ11
45 DQ12
46 DQ13
REFRESH COLUMN
COLUMN DECODER
48 DQ14
COUNTER COUNTER
R
O 49 DQ15
W
CE CI XMODE
D CELL ARRAY
E BANK #1
39 38 41
C
O
D
E
14 LDQM
R
36 UDQM
SENSE AMPLIFIER
37 DO
36 RERR
21 RDATA
24 SDIN
IC6: SN74AHC1G08DCKR
16 RMCK
2-input positive-AND gate
17
RBCK
20 RLRCK
22 SBCK
23 SLRCK A 1 5 Vcc
B 2
GND 3 4 Y
IC8: SN74LV245APWR
Octal bus transceivers with 3-state outputs
DIR 1 20 Vcc
A1 2 19 OE
A2 3 18 B1
C67x TM CPU
Control
A3 4 17 B2
Registers
Control
Logic A4 5 16 B3
Data Path B
Test
B Register File A5 6 15 B4
In-Circuit
Emulation
A6 7 14 B5
.D2 .M2t .S2t .L2t Interrupt
Control
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
Power-Down
Logic
DQ0–DQ15 (A-1)
RY/ BY#
Sector Switches
Erase Vo ltage Input/Output
Generator Buffers
State
Control
Command
Register
PGM Voltage
Generator
Data
Chip Enable
STB Lat ch
Output Enable
Logic
Y-Decoder Y- Gating
STB
V Detector Timer
CC
Cell Matrix
X- Decoder
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 V
SS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7
42 DQ6
A8 8 41 DQ13
NC 9 40 DQ5
NC 10 39 DQ12
WE# 11 38 DQ4
RESET# 12 37 V
CC
NC 13 36 DQ11
NC 14
35 DQ3
RY/BY# 15 34
DQ10
NC 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
V
A3 22 27 SS
A2 23
26 CE#
A1 24 25 A0
55