Ic Data - Yamaha YSP-900 Service Manual

YSP-900
I IC DATA
IC24 : M30626FJPFP (DSP P.C.B)
16-bit Microprocessor
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
42
8 8 8
Port P0
Port P1 Port P2 Port P3
(4)
<VCC2 ports>
Internal peripheral functions
A/D converter
(10 bits
X
Timer (16-bit)
Expandable up to 26 channels)
Output (timer A): 5
UART or
Input (timer B): 6
clock synchronous serial I/O
(8 bits
X
Three-phase motor
control circuit
CRC arithmetic circuit (CCITT )
(Polynomial : X
M16C/60 series16-bit CPU core
R0H R0L
Watchdog timer
R1H R1L
(15 bits)
R2
R3
DMAC
A0
(2 channels)
A1
FB
D/A converter
(8 bits X 2 channels)
(4)
<VCC1 ports>
<VCC2 ports>
Port P11 Port P14 Port P12
(3) (3) (3)
8 2 8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
8 8 8 8
Port P4 Port P5 Port P6
(4)
<VCC1 ports>
System clock
8 channels generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
3 channels)
On-chip oscillator
Clock synchronous serial I/O
16 12 5
+X +X +1)
(8 bits 2 channels)
X
Memory
SB (1)
ROM
USP
ISP
(2)
RAM
INTB
PC
FLG
Multiplier
(4)
Port P13
(3)
8
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1