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Block diagrams
DIGITAL 0 2
PHY_RESET[L]
5
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
SDRAM_DQ0 to 15
4
3
2
1
A
2-5
IEEE1394
controller
IC1801
IEEE1394 section (SHEET 2)
SDRAM_DQ16 to 31
RA1613 to
RA1609 to
RA1612
SDRAM_A0 to 15
RA1625 to
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_DQM0 to 3
SDRAM_DQS0 to 3
SDRAM_CLK0,1
SDRAM_CLK_L0,1
Media
processor
IC1401
IC1406
IC1407
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] F_PROT[H] E5_RESET[L]
Media processor (SHEET 4)
B
TPA+ TPA- TPB+ TPB-
DDR_DQ16 to 31
RA1616
DDR SDRAM
DDR_DQ0 to 15
IC1601
RA1628
R1601 to
R1604
DDR_DQM0 to 3
R1653 to
DDR_DQS0 to 3
R1660
DDR_CLK0,1
DDR_CLK_L0,1
R1613 to
R1616
DDR SDRAM section (SHEET 3)
ATA_DMAACK[L] ATA_INTRQ ATA_ADD1 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
SYS_RESET[L] VIDEO_RXD
K_BUS_CLK K_BUS_REQ K_BUS_IN/OUT
VIDEO_RST[L] SPI_MOSI SPI_CLK VIDEO_CS
DDR SDRAM
IC1602
DDR_BA1,2
DDR_A0 to 12
DDR_CKE
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
C
J4112
IEEE1394
terminal
D
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