Sharp CD-C1W Service Manual page 49

IC2 VHiLC78623K-1:Servo/Signal Control(LC78623K) (2/2)
Terminal Name Input/Output
Pin No.
49* PW
50* SFSY
51 SBCK
52* FSX
53 WRQ
54 RWC
55 SQOUT
56 COIN
57 CQCK
58 RES
59* TST11
60* 16M
61 4M
62 TEST5
63 CS
64 TEST1
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
IC2 VHiLC78623K-1:Servo/Signal Control(LC78623K) (2/2)
9
DEFI
1
Slice level
control
EFMIN
10
Sync detection
FSEQ
22
EFM demodulation
CLV+
12
CLV
Digital servo
CLV- 13
V/P
14
PW 49
Subcode division
SBCK
51
QCRC
SBSY 47
SFSY
50
CS
63
µ COM
WRQ 53
Interface
SQOUT 55
CQCK 57
COIN
56
Servo commander
RWC
54
15 16 17 20 19 58
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Output Output terminal of subcodes P, A, R, S, T, U and W.
Output Output terminal of synchronous signal of subcode frame. It drops when subcode stands by.
Input Clock input terminal to read subcode. Schmit input (Connected to 0V when not used.)
Output Output terminal of synchronous signal of 7.35kHz divided from quartz oscillation.
Output Output terminal to stand by output of subcode Q.
Input Input terminal of read/write. Schmit input.
Output Output terminal of subcode Q.
Input Command input terminal from microcomputer.
Input Clock input terminal to fetch command input, or pick up subcode from SQOUT. Schmit input
Input Reset input terminal of LC78622. When turning on power, set it at "L".
Output Output terminal for test. Used in the open state ("L" output as ordinary).
Output Output terminal of 16.9344Hz.
Output Output terminal of 4.2336MHz.
Input Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
Input Chip selection input terminal. Pull-down resistor is integrated.
Connected to 0when not controlled.
Input Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
6 4 3 5 7 21 2
VCO colck oscillation
clock control
Flag processing of C1/C2
error detection and correction
General-use port
18 24 25 26 27 28
24 48
Figure 49 BLOCK DIAGRAM OF IC
Function
59 64 11 32 33 62 23 8
2 K X 8 b i t
R A M
Interpolation mute
X4 oversampling
XTAL system timing
generator
60 61 46 52 45 44 43 39 41 42
– 49 –
CD-C1W,CP-C1W
RAM address
generator
30
Bilingual
Digital OUT
31
Digital
attenuator
digital filter
34
1 b i t D A C
L . P . F
35 38 36
40 37
C2F
DOUT
PCCL