Asus AAEON GENE-SKU6 User Manual
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Asus AAEON GENE-SKU6 User Manual

3.5” subcompact board
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GENE-SKU6
3.5" Subcompact Board
User's Manual 7
th
Ed
Last Updated: June 12, 2018

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Summary of Contents for Asus AAEON GENE-SKU6

  • Page 1 GENE-SKU6 3.5” Subcompact Board User’s Manual 7 Last Updated: June 12, 2018...
  • Page 2 Copyright Notice This document is copyrighted, 20188. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation  Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity GENE-SKU6 with heat spreader  Product DVD with User’s Manual (in pdf) and drivers  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○ 连接器及线材...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................7 Thermal Solution ..................... 8 2.3.1 GENE-SKU6-HSK01 ................8 2.3.2 GENE-SKU6-HSK02 ................9 2.3.3 GENE-SKU6-HSK03 ................
  • Page 12 2.7.2 DVI-I (Digital and Analog) (CN3) ............. 22 2.7.3 DP Port (CN5) ..................23 2.7.4 LVDS Port (CN6) .................. 24 2.7.5 LVDS Port Inverter / Backlight Connector (CN7) ......26 2.7.6 SPI Debug Port (CN8)................. 26 2.7.7 LAN (RJ-45) Port1 (CN9) ..............27 2.7.8 LAN (RJ-45) Port2 (CN10) ..............
  • Page 13 2.7.30 CPU Fan (CN36) ................... 56 Chapter 3 - AMI BIOS Setup ....................57 System Test and Initialization ................58 AMI BIOS Setup ..................... 59 Setup submenu: Main ..................60 Setup submenu: Advanced .................. 61 3.4.1 Advanced: CPU Management ............63 3.4.2 Advanced: SATA Configuration ............
  • Page 14 Appendix A - Watchdog Timer Programming ..............97 Watchdog Timer Registers .................. 98 Watchdog Sample Program ................99 Appendix B - I/O Information ..................... 102 I/O Address Map ....................103 Memory Address Map ..................104 IRQ Mapping Chart ..................... 105 Appendix C –...

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    Specifications System 3.5” Form Factor  Intel ® Core™ i3/i5/i7 processor SoC  Up to 2.4/3.0 GHz CPU Frequency  Intel ® Core™ i3/i5/i7 processor SoC Chipset  DDR4 1866/2133 SODIMM x 1 Memory Type  16 GB Max Memory Capacity ...
  • Page 17 Display VGA/LCD Controller Intel ® Core™ i3/i5/i7 processor SoC  DVI, CRT/DP , LVDS Video Output  (CRT is shared with DP , and default is DP) Backlight Inverter Supply  Intel I210, 10/100/1000Base , RJ-45 x 2 Ethernet  High definition audio interface Audio ...

  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 19: Dimensions

    Dimensions Component Side Component Side Chapter 2 – Hardware Information...
  • Page 20 Solder Side (with heat spreader) Solder Side Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Component Side Chapter 2 – Hardware Information...

  • Page 22: Thermal Solution

    Thermal Solution 2.3.1 GENE-SKU6-HSK01 Heatsink used with a heat spreader Recommend to be used with the system cooler and the system air flow > 7CFM Chapter 2 – Hardware Information...

  • Page 23: Gene-Sku6-Hsk02

    2.3.2 GENE-SKU6-HSK02 One shape heatsink – no need to use a heat spreader Extended temperature SKUs are tested using the GENE-SKU6-HSK02 thermal solution and under UEFI mode. Chapter 2 – Hardware Information...

  • Page 24: Gene-Sku6-Hsk03

    2.3.3 GENE-SKU6-HSK03 Heatsink for DRAM Chapter 2 – Hardware Information...

  • Page 25: Gene-Sku6-Fan01

    2.3.4 GENE-SKU6-FAN01 Cooler used with a heat spreader Chapter 2 – Hardware Information...

  • Page 26: Assembly Options

    Assembly Options Option 1 Chapter 2 – Hardware Information...
  • Page 27 Option 2 Chapter 2 – Hardware Information...
  • Page 28 Option 3 Chapter 2 – Hardware Information...

  • Page 29: Block Diagram

    Block Diagram Chapter 2 – Hardware Information...

  • Page 30: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function Clear CMOS Jumper LVDS Port Backlight Inverter VCC Selection LVDS Port Backlight Lightness Control Mode Selection LVDS Port Operating VDD Selection mSATA/Mini-Card Operating VCC Selection Touch Screen 4/5/8-wire Mode Selection...

  • Page 31: Clear Cmos Jumper (Jp1)

    2.6.1 Clear CMOS Jumper (JP1) Normal (Default) Clear CMOS 2.6.2 LVDS Port Backlight Inverter VCC Selection (JP2) +12V +5V (Default) 2.6.3 LVDS Port Backlight Lightness Control Mode Selection (JP3) 1 2 3 VR Mode (Default) PWM Mode 2.6.4 LVDS Port Operating VDD Selection (JP4) 1 2 3 +3.3V (Default) Chapter 2 –...

  • Page 32: Msata/ Mini-Card Operating Vcc Selection (Jp5)

    2.6.5 mSATA/ Mini-Card Operating VCC Selection (JP5) 1 2 3 mSATA (Default) Mini-Card 2.6.6 Touch Screen 4,5,8 Wire Selection (JP6) 1 2 3 4/8 WireS Mode (Default) 5 Wires Mode 2.6.7 Auto Power Button Enable/Disable Selection (JP7) 1 2 3 Disable Enable (Default) * When disabled, use power button JP10(1-2) to power on the system.

  • Page 33: Com2 Pin8 Function Selection (Jp9)

    2.6.9 COM2 Pin8 Function Selection (JP9) Ring (Default) +12V 2.6.10 Front Panel Connector (JP10) Pin Name Pin Name PWR_BTN- PWR_BTN+ HDD_LED- HDD_LED+ SPEAKER- SPEAKER+ PWR_LED- PWR_LED+ H/W RESET- H/W RESET+ 2.6.11 COM4 Pin8 Function Selection (JP11) Ring (Default) +12V Chapter 2 – Hardware Information...

  • Page 34: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Battery DVI-I (Digital and Analog) DP Port LVDS Port LVDS Port Inverter / Backlight Connector SPI Debug Port LAN (RJ-45) Port1 CN10 LAN (RJ-45) Port2...
  • Page 35 CN28 COM Port 3 CN29 LPC Port CN30 External Power Input CN32 +5VSB Output w/SMBus CN33 External +5VSB Input CN35 BIO Connector CN36 CPU FAN Chapter 2 – Hardware Information...

  • Page 36: Battery (Cn1)

    2.7.1 Battery (CN1) Pin Name Signal Type Signal level +3.3V 3.3V 2.7.2 DVI-I (Digital and Analog) (CN3) Pin Name Signal Type Signal Level DVI_D2- DVI_D2+ VGA_DDC_CLK VGA_DDC_DAT VGA_VSYNC DVI_D1- DVI_D1+ DVI_D0- DVI_D0+ Chapter 2 – Hardware Information...

  • Page 37: Dp Port (Cn5)

    DVI_CLK+ DVI_CLK- VGA_RED VGA_GREEN VGA_BLUE VGA_HSYNC 2.7.3 DP Port (CN5) Pin Name Signal Type Signal Level DP_D0+ DIFF DP_D0- DIFF DP_D1+ DIFF DP_D1- DIFF DP_D2+ DIFF DP_D2- DIFF DP_D3+ DIFF DP_D3- DIFF DP_AUX+ DIFF Chapter 2 – Hardware Information...

  • Page 38: Lvds Port (Cn6)

    DP_AUX- DIFF HPLG_DETECT 2.7.4 LVDS Port (CN6) *LVDS LCD_PWR can be set to +3.3V or +5V by JP4 Pin Name Signal Type Signal Level BKL_ENABLE BKL_CONTROL LCD_PWR +3.3V/+5V LVDS_A_CLK- DIFF LVDS_A_CLK+ DIFF LCD_PWR +3.3V/+5V LVDS_DA0- DIFF LVDS_DA0+ DIFF Chapter 2 – Hardware Information...
  • Page 39 LVDS_DA1- DIFF LVDS_DA1+ DIFF LVDS_DA2- DIFF LVDS_DA2+ DIFF LVDS_DA3- DIFF LVDS_DA3+ DIFF DDC_DATA +3.3V DDC_CLK +3.3V LVDS_DB0- DIFF LVDS_DB0+ DIFF LVDS_DB1- DIFF LVDS_DB1+ DIFF LVDS_DB2- DIFF LVDS_DB2+ DIFF LVDS_DB3- DIFF LVDS_DB3+ DIFF LCD_PWR +3.3V/+5V LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF Chapter 2 – Hardware Information...

  • Page 40: Lvds Port Inverter / Backlight Connector (Cn7)

    2.7.5 LVDS Port Inverter / Backlight Connector (CN7) Pin Name Signal Type Signal level BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE * LVDS BKL_PWR can be set to +5V or +12V by JP2 * LVDS BKL_CONTROL can be set by JP3 2.7.6 SPI Debug Port (CN8) Pin Name Signal Type...

  • Page 41: Lan (Rj-45) Port1 (Cn9)

    2.7.7 LAN (RJ-45) Port1 (CN9) ACT/LINK SPEED Pin Name Signal Type Signal level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF 2.7.8 LAN (RJ-45) Port2 (CN10) Pin Name Signal Type Signal level MDI0+ DIFF MDI0-...

  • Page 42: Mini-Card Slot (Full-Mini Card) (Cn11)

    MDI3+ DIFF MDI3- DIFF 2.7.9 Mini-Card Slot (Full-Mini Card) (CN11) Pin Name Signal Type Signal level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V Chapter 2 – Hardware Information...
  • Page 43 PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V Chapter 2 – Hardware Information...

  • Page 44: Micro Sim Card Socket (Cn12)

    +3.3VSB +3.3V 2.7.10 Micro SIM Card Socket (CN12) Pin Name Signal Type Signal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA 2.7.11 Mini-Card Slot (Half-Mini Card) (CN13) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# Chapter 2 – Hardware Information...
  • Page 45 PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX-/mSATA_RX+ DIFF +3.3VSB +3.3V PCIE_RX+/mSATA_RX- DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX-/mSATA_TX- DIFF SMB_DATA +3.3V PCIE_TX+/mSATA_TX+ DIFF Chapter 2 – Hardware Information...
  • Page 46 USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V +3.3VSB +3.3V * CN13 can be selected for Mini-Card or mSATA by changing BIOS Chapter 2 – Hardware Information...

  • Page 47: Sata Port 1 (Cn14)

    2.7.12 SATA Port 1 (CN14) Pin Name Signal Type Signal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF 2.7.13 +5V Output for SATA HDD (CN15) Pin Name Signal Type Signal Level Chapter 2 – Hardware Information...

  • Page 48: Usb 3.0 Ports (Cn18)

    2.7.14 USB 3.0 Ports (CN18) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF Chapter 2 – Hardware Information...

  • Page 49: Usb 3.0 Ports (Cn19)

    2.7.15 USB 3.0 Ports (CN19) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF Chapter 2 – Hardware Information...

  • Page 50: Usb 2.0 Port (Cn20)

    2.7.16 USB 2.0 Port (CN20) +5VSB USB3_D- USB3_D+ Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF 2.7.17 USB 2.0 Port (CN21) Pin Name Signal Type Signal Level +5VSB USB_D- DIFF USB_D+ DIFF G ND Chapter 2 – Hardware Information...

  • Page 51: Audio I/O Port (Cn22)

    2.7.18 Audio I/O Port (CN22) Pin Name Signal Type Signal Level MIC_L MIC_R GND_AUDIO LINE_L_IN LINE_R_IN GND_AUDIO LEFT_OUT GND_AUDIO RIGHT_OUT +5V_AUDIO Chapter 2 – Hardware Information...

  • Page 52: Touchscreen Connector (Cn23)

    2.7.19 Touchscreen Connector (CN23) * Touch mode can be set by JP6 4-Wire Pin Name Signal Type Signal Level BOTTOM LEFT RIGHT 4 Wires 5 Wires UL(Y) BOTTOM UR(H) LEFT LL(L) RIGHT LR(X) SENSE(S) Chapter 2 – Hardware Information...
  • Page 53 5-Wire Pin Name Signal Type Signal Level UL(Y) UR(H) LL(L) LR(X) SENSE(S) 8-Wire Pin Name Signal Type Signal Level TOP EXCITE BOTTOM EXCITE LEFT EXCITE RIGHT EXCITE TOP SENSE BOTTOM SENSE LEFT SENSE Chapter 2 – Hardware Information...

  • Page 54: Digital I/O Port (Cn24)

    RIGHT SENSE 2.7.20 Digital I/O Port (CN24) DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Pin Name Signal Type Signal Level DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Chapter 2 – Hardware Information...

  • Page 55: Com Port 1 (Cn25)

    2.7.21 COM Port 1 (CN25) Pin Name Signal Type Signal Level ±9V ±9V ±9V Chapter 2 – Hardware Information...

  • Page 56: Com Port 4 (Cn26)

    2.7.22 COM Port 4 (CN26) RS-232 Pin Name Signal Type Signal Level ±5V ±5V ±5V RI/+5V/+12V IN/ PWR +5V/+12V Chapter 2 – Hardware Information...
  • Page 57 RS422_TX- RS422_TX+ RS422_RX+ RS422_RX- NC/+5V/+12V RS-422 Pin Name Signal Type Signal Level RS422_TX- ±5V RS422_TX+ ±5V RS422_RX+ RS422_RX- NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...
  • Page 58 RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V NC/+5V/+12V +5V/+12V * COM4 RS-232/422/485 can be set by BIOS setting. Default is RS-232. * Pin 8 function can be set by JP11. Chapter 2 – Hardware Information...

  • Page 59: Com Port 2 (Cn27)

    2.7.23 COM Port 2 (CN27) RS-232 Pin Name Signal Type Signal Level ±5V ±5V ±5V RI/+5V/+12V IN/ PWR +5V/+12V Chapter 2 – Hardware Information...
  • Page 60 RS-422 Pin Name Signal Type Signal Level RS422_TX- ±5V RS422_TX+ ±5V RS422_RX+ RS422_RX- NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...
  • Page 61 RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V NC/+5V/+12V +5V/+12V * COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. * Pin 8 function can be set by JP9. Chapter 2 – Hardware Information...

  • Page 62: Com Port 3 (Cn28)

    2.7.24 COM Port 3 (CN28) RS-232 Pin Name Signal Type Signal Level ±5V ±5V ±5V RI/+5V/+12V IN/ PWR +5V/+12V Chapter 2 – Hardware Information...
  • Page 63 RS-422 Pin Name Signal Type Signal Level RS422_TX- ±5V RS422_TX+ ±5V RS422_RX+ RS422_RX- NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...
  • Page 64 RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V NC/+5V/+12V +5V/+12V * COM3 RS-232/422/485 can be set by BIOS setting. Default is RS-232. * Pin 8 function can be set by JP8. Chapter 2 – Hardware Information...

  • Page 65: Lpc Port (Cn29)

    2.7.25 LPC Port (CN29) Pin Name Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V +3.3V LFRAME# LRESET# +3.3V LCLK LDRQ0 LDRQ1 SERIRQ +3.3V Chapter 2 – Hardware Information...

  • Page 66: External Power Input (Cn30)

    2.7.26 External Power Input (CN30) Pin Name Signal Type Signal Level +12V +9~+36V (or +12V) 2.7.27 +5VSB Output w/SMBus (CN32) Pin Name Signal Type Signal Level SMB_DATA +3.3V SMB_CLK +3.3V PS_ON# +3.3V +5VSB Chapter 2 – Hardware Information...

  • Page 67: External +5Vsb Input (Cn33)

    2.7.28 External +5VSB Input (CN33) Pin Name Signal Type Signal Level PS_ON# +3.3V +5VSB ※ Since every power supply discharge design is different, we recommend restart after power off 3seconds to make sure ATX power is full discharge. Or make sure 5V standby power have been discharged under 2V.
  • Page 68 PCIE2_RX- PCIE2_TX+ PCIE2_RX+ PS_ON# +5V_Dual +5V_Dual +5V_Dual +5V_Dual PCIE_CLK+ PLT_RST# PCIE_CLK- Chapter 2 – Hardware Information...
  • Page 69 USB 3.0_TX- USB 3.0_TX+ USB 2.0_D- USB 2.0_D+ USB 3.0_RX- USB 3.0_RX+ SMB_CLK SMB_DATA PCIE_WAKE# USB 2.0_OC# USB 2.0_OC# Chapter 2 – Hardware Information...

  • Page 70: Cpu Fan (Cn36)

    LPC_AD0 LPC_FRAME# LPC_AD1 SERIRQ# LPC_AD2 LPC_AD3 GPIO Audio_GND LPC_CLK Audio_OUT_L PME# Audio_OUT_R 2.7.30 CPU Fan (CN36) Pin Name Signal Type Signal Level FAN_POWER +12V FAN_TAC Chapter 2 – Hardware Information...

  • Page 71: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 72: System Test And Initialization

    System Test and Initialization The board uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 73: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 74: Setup Submenu: Main

    Setup submenu: Main Press ‘Delete’ Key to enter Setup Options summary: (default setting) System Date Day MM:DD:YYYY Change the month, year and century. The ‘Day’ is changed automatically. System Time HH : MM : SS Change the clock of the system. Chapter 3 –...

  • Page 75: Setup Submenu: Advanced

    Setup submenu: Advanced Options summary: (default setting) CPU Configuration CPU Configuration Parameters Trusted Computing Trusted Computing Settings SATA Configuration SATA Device Options Settings Hardware Monitor Monitor hardware status SIO Configuration Super IO Configuration Parameters Chapter 3 – AMI BIOS Setup...
  • Page 76 USB Configuration USB Configuration Parameters CSM Configuration CSM Enable/Disable, Option ROM execution setting. Digital IO Port Configuration DIO configuration Power Management System ACPI/Power Mode/Wake Event Configuration Chapter 3 – AMI BIOS Setup...

  • Page 77: Advanced: Cpu Management

    3.4.1 Advanced: CPU Management Options summary: (default setting) Hyper-threading Enabled Disabled Enable/Disable Intel Hyper-threading(HT) feature. Intel Virtualization Enabled Technology Disabled When enabled, a VMM can utilize the additional hardware capabilities provide by Vanderpool Technology CPU C State Report Enabled Disabled Enable/Disable CPU C state report to OS Chapter 3 –...
  • Page 78 Intel(R) SpeedStep(tm) Enabled Disabled Enable/Disable Intel SpeedStep feature. Turbo Mode Enabled Disabled En/Disable Turbo mode. This feature is only available when Intel SpeedStep enabled. Chapter 3 – AMI BIOS Setup...

  • Page 79: Advanced: Sata Configuration

    3.4.2 Advanced: SATA Configuration Options summary: (default setting) SATA Speed Support Enabled Disabled Enable or disable SATA Device Serial ATA Port/mSATA Port Enabled Disabled Enabled/Disabled Serial ATA Port/mSATA Port Serial ATA Port/mSATA Port Enabled Hot Plug Disabled Designated specified port as Hot Pluggable. Chapter 3 –...

  • Page 80: Advanced: Usb Configuration

    3.4.3 Advanced: USB Configuration Options summary: (default setting) Legacy USB Support Enabled Disabled Auto Enables BIOS Support for Legacy USB Support. When enabled, USB can be functional in legacy environment like DOS. AUTO option disables legacy support if no USB devices are connected.

  • Page 81: Advanced: Sio Configuration

    3.4.4 Advanced: SIO Configuration Options summary: (default setting) Serial Port 1/2/3/4 Configuration Set Parameters of Serial Port 1/2/3/4 Chapter 3 – AMI BIOS Setup...

  • Page 82: Sio Configuration: Serial Port 1-4 Configuration

    3.4.4.1 SIO Configuration: Serial Port 1-4 Configuration Options summary: (default setting) Use This Device Disabled Enabled En/Disable specified serial port. Change Settings Use Automatic Settings (COM1) IO=3F8h; IRQ=4; IO=2F8h; IRQ=3; Change Settings Use Automatic Settings (COM2) IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Change Settings Use Automatic Settings Chapter 3 –...
  • Page 83 (COM3) IO=3E8h; IRQ=11; IO=2E8h; IRQ=11; Change Settings Use Automatic Settings (COM4) IO=2E8h; IRQ=11; IO=3E8h; IRQ=11; Select a resource setting for Super IO device. Mode RS232 RS422 RS485 Configure COM operated as RS232, RS422 or RS485. Only COM3 and COM4 support this function.

  • Page 84: Advanced: Hardware Monitor

    3.4.5 Advanced: Hardware Monitor Options summary: (default setting) Smart Fan Disabled Enabled En/Disable specified Smart Fan. Chapter 3 – AMI BIOS Setup...

  • Page 85: Hardware Monitor: Smart Fan Configuration

    3.4.5.1 Hardware Monitor: Smart Fan Configuration Options summary: (default setting) Fan Mode Manual Duty Auto Duty Smart Fan Mode Select Manual Duty Mode Manual mode fan control, user can write expected duty cycle (PWM fan type) 1 – 100 Temperature Source Select the monitored temperature source for this fan.
  • Page 86 Duty Cycle 3 Duty Cycle 4 Duty Cycle 5 Fan speed control for each temperature region. User can write expected duty cycle (PWM fan type) 1 – 100 Temperature 1 Temperature 2 Temperature 3 Temperature 4 Definition of temperature region. User can write expected temperature boundary 1 – Note: Optional support for PWM mode is available on request.

  • Page 87: Advanced: Csm Configuration

    3.4.6 Advanced: CSM Configuration Options summary: (default setting) CSM Support Enabled Disabled Enable/Disable for CSM Support Boot option filter UEFI and Legacy Legacy only UEFI only This option controls Legacy/UEFI boot option priority Network/PXE Do not launch UEFI Legacy Chapter 3 – AMI BIOS Setup...
  • Page 88 Controls the execution of UEFI and Legacy PXE OpROM Storage Do not launch UEFI Legacy Controls the execution of UEFI and Legacy Storage OpROM Video Do not launch UEFI Legacy Controls the execution of UEFI and Legacy Video OpROM Chapter 3 – AMI BIOS Setup...

  • Page 89: Advanced: Power Management

    3.4.7 Advanced: Power Management Options summary: (default setting) ATX Type Power Mode AT Type Select system power mode Enabled Power Saving (ERP) Control Disabled Enabled or disabled ERP feature for power saving in S5 state. Power Off Restore AC Power Loss Power on Late State Select AC power state when power is re-applied after a power failure...
  • Page 90 RTC wake system from S5 Disabled Fixed Time Dynamic Time Enable system to wake from S5 using RTC alarm. Wake up day 0-31 Select 0 for daily system wake up 1-31 for which day of the month that you would like the system to wake up Wake up hour 0-23...

  • Page 91: Advanced: Digital Io Port Configuration

    3.4.8 Advanced: Digital IO Port Configuration Options summary: (default setting) DIO Port1/2/3/4 Input Output Set DIO Port1/2/3/4 as Input or Output DIO Port5/6/7/8 Input Output Set GPIO3/GPIO4 as Input or Output Output Level Set GPIO Level when used as Output Chapter 3 –...

  • Page 92: Setup Submenu: Chipset

    Setup submenu: Chipset Options summary: (default setting) System Agent (SA) Configuration System Agent (SA) Parameters. PCH-IO Configuration PCH Parameters Chapter 3 – AMI BIOS Setup...

  • Page 93: Chipset: System Agent (Sa) Configuration

    3.5.1 Chipset: System Agent (SA) Configuration Options summary: (default setting) Graphics Configuration Graphics Configuration Chapter 3 – AMI BIOS Setup...

  • Page 94: System Agent (Sa) Configuration: Graphics Configuration

    3.5.1.1 System Agent (SA) Configuration: Graphics Configuration Options summary: (default setting) Primary IGFX Boot Display VBIOS Default CRT/DP LVDS Select Primary boot display device Secondary Boot Display Disabled CRT/DP LVDS Select Primary boot display device Chapter 3 – AMI BIOS Setup...

  • Page 95: Graphics Configuration: Lvds Panel Configuration

    LVDS Panel Configuration Config LVDS panel parameters. 3.5.1.2 Graphics Configuration: LVDS Panel Configuration Options summary: (default setting) LVDS Disabled Enabled Enable or Disable LVDS interface Panel Type 640x480@60Hz 800x480@60Hz 800x600@60Hz 1024x600@60Hz Chapter 3 – AMI BIOS Setup...
  • Page 96 1024x768@60Hz 1280x768@60Hz 1280x800@60Hz 1280x1024@60Hz 1366x768@60Hz 1440x900@60Hz 1600x1200@60Hz 1920x1080@60Hz 1920x1200@60Hz Select panel resolution. Color Depth 18-Bit 24-Bit 36-Bit 48-Bit Select color depth of the panel Backlight Type Inverted Normal Select Backlight control type. Inverted: Brightest for low PWM duty cycle and low voltage. Normal: Brightest for high PWM duty cycle and high voltage.
  • Page 97 Select Backlight Level Backlight PWM Freq 100Hz 200Hz 220Hz 500Hz 1KHz 2.2KHz 6.5KHz Select PWM frequency of backlight control signal. Chapter 3 – AMI BIOS Setup...

  • Page 98: Chipset: Pch-Io Configuration

    3.5.2 Chipset: PCH-IO Configuration Options summary: (default setting) HD Audio Disabled Enabled Enable or disabled Azalia device for audio function. Full-MiniCard Slot Disabled Enabled Control the full-size minicard slot PCIe Speed Auto Gen1 Gen2 Gen3 Chapter 3 – AMI BIOS Setup...
  • Page 99 PCIe Gen Speed for full-size minicard. Half-MiniCard Slot mSATA Function PCIe Select function enabled for Half-MiniCard(CN13) Slot Half-MiniCard Slot Disabled Enabled Control the full-size minicard slot PCIe Speed Auto Gen1 Gen2 Gen3 PCIe Gen Speed for half-size minicard. Chapter 3 – AMI BIOS Setup...

  • Page 100: Setup Submenu: Security

    Setup submenu: Security Options summary: (default setting) Administrator Password/ Not set User Password Change User/Administrator Password If an Administrator Password is set, it will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility.
  • Page 101 Enter to confirm your entry, after which you will be prompted to retype your password for a final confirmation. Press Enter again after you have retyped it correctly. Removing the Password Highlight this item and type in the current password. At the next dialog box press Enter to disable password protection.

  • Page 102: Setup Submenu: Boot

    Setup submenu: Boot Options summary: (default setting) Quiet Boot Disabled Enabled En/Disable showing boot logo. Boot Option #X/ XXXX Drive BBS Priorities The order of boot priorities. Chapter 3 – AMI BIOS Setup...

  • Page 103: Boot: Bbs Priorities

    3.7.1 Boot: BBS Priorities Options summary: (default setting) Boot Option #x Disabled Device name Sets the system boot order Chapter 3 – AMI BIOS Setup...

  • Page 104: Setup Submenu: Save & Exit

    Setup submenu: Save & Exit Options summary: (default setting) Save Changes and Reset Reset the system after saving the changes Discard Changes and Exit Reset system setup without saving any changes Restore Defaults Restore/Load Default values for all the setup options. Chapter 3 –...

  • Page 105: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 106: Product Cd/Dvd

    Product CD/DVD The GENE-SKU6 comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers. Step 1 –...
  • Page 107 Follow the instructions Drivers will be installed automatically Step 5 – Install USB 3.0 Driver (Windows 7 only) Open the Step5 - USB3.0 folder followed by Setup.exe Follow the instructions Drivers will be installed automatically Step 6 – Install TPM 2.0 Driver (Windows 7 only) Open the Step6 TPM 2.0 folder followed by the .msu file Follow the instructions Drivers will be installed automatically...
  • Page 108 Step 8 – Install Serial Port Drivers For Windows 7: Change User Account Control settings to Never notify Reboot and log in as administrator Chapter 4 – Driver Installation...
  • Page 109 Run patch.bat as administrator For Windows 8/10: Click on the Step8 - Serial Port Driver (Optional) folder and select your OS Open the setup.exe file in the folder Follow the instructions Drivers will be installed automatically Chapter 4 – Driver Installation...

  • Page 110: Note On Ehci

    Note on EHCI With the EHCI controller no longer available on the 6th Gen Intel Core™ ® platforms, it is recommended to install Windows 7 through a SATA bus, eg SATA DVD-ROM, or patch the xHCI driver onto an installation media for Windows 7.

  • Page 111: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 112: Watchdog Timer Registers

    Watchdog Timer Registers Table 1 : Watch dog relative IO address Default Value Note I/O Base I/O Base address for Watchdog operation. 0xA10 Address This address is assigned by SIO LDN7, register 0x60-0x61. Table 2 : Watchdog relative register table Register Offset BitNum...

  • Page 113: Watchdog Sample Program

    A.2 Watchdog Sample Program ****************************************************************************** // WDT I/O operation relative definition (Please reference to Table 1) #define WDTAddr 0x510 // WDT I/O base address Void WDTWriteByte(byte Register, byte Value); byte WDTReadByte(byte Register); Void WDTSetReg(byte Register, byte Bit, byte Val); // Watch Dog relative definition (Please reference to Table 2) #define DevReg 0x00 // Device configuration register #define WDTRstBit 0x80 // Watchdog WDTRST# (Bit7)
  • Page 114 VOID AaeonWDTEnable (){ WDTEnableDisable(1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (byte Counter, BOOLEAN Unit){ // Disable WDT counting WDTEnableDisable(0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(Timer, Unit); VOID WDTEnableDisable(byte Value){ If (Value == 1) WDTSetBit(TimerReg, EnableBit, 1); else WDTSetBit(TimerReg, EnableBit, 0);...
  • Page 115 VOID WDTWriteByte(byte Register, byte Value){ IOWriteByte(WDTAddr+Register, Value); byte WDTReadByte(byte Register){ return IOReadByte(WDTAddr+Register); VOID WDTSetBit(byte Register, byte Bit, byte Val){ byte TmpValue; TmpValue = WDTReadByte(Register); TmpValue &= ~(1 << Bit); TmpValue |= Val << Bit; WDTWriteByte(Register, TmpValue); ******************************************************************************* Appendix A – Watchdog Timer Programming...

  • Page 116: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 117: I/O Address Map

    I/O Address Map * There are no PS/2 ports on the GENE-SKU6, hence the exclamation marks. Appendix B – I/O Information...

  • Page 118: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 119: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...

  • Page 120: Appendix C - Electrical Specifications For I/O Ports

    Appendix C Appendix C – Electrical Specifications for I/O Ports...

  • Page 121: Electrical Specifications For I/O Ports

    Electrical Specifications for I/O Ports Reference Signal Name Rate Output DVI Port +5V/1A (reserved) DP port +3.3V +3.3V/1A +3.3V/2A or LVDS Port +3.3V/+5V +5V/2A LVDS Port Inverter / +5V/1.5A or +5V/+12V Backlight Connector +12V/1.5A Mini-Card Slot +3.3VSB +3.3V/1.1A CN11 (Full-Mini Card) +1.5V +1.5V/0.375A Mini-Card Slot...
  • Page 122 Audio I/O Port CN22 +5V/1A Digital IO Port CN24 +5V/1A +5V/0.5A or COM Port 4 CN26 +5V/+12V +12V/0.5A +5V/0.5A or COM Port 2 CN27 +5V/+12V +12V/0.5A +5V/0.5A or COM Port 3 CN28 +5V/+12V +12V/0.5A LPC Port CN29 +3.3V +3.3V/0.5A CPU FAN CN36 +12V +12V/0.5A...

  • Page 123: Appendix D - Digital I/O Ports

    Appendix D Appendix D – Digital I/O Ports...

  • Page 124: Electrical Specifications For Digital I/O Ports

    Electrical Specifications for Digital I/O Ports Table 1 : Digital Input/Output Pin Electrical Specification Input Threshold Output Voltage Voltage Type Note High High DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Note: All DIO pins are 5V tolerant in input mode. Appendix D –...

  • Page 125: Di/O Programming

    DI/O Programming GENE-SKU6 utilizes FINTEK F81866D chipset as its Digital I/O controller. Below are the procedures to complete its configuration and the AAEON initial DI/O program is also attached, based on which you can develop customized program to fit your application. There are three steps to complete the configuration setup: (1) Enter the MB PnP Mode (2) Modify the data of configuration registers...

  • Page 126: Digital I/O Register

    Digital I/O Register Table 2 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F) 0x2F or 0x4F Table 3 : Digital Input/Output relative register table Register Note DIO0 Direction...

  • Page 127: Digital I/O Sample Program

    Digital I/O Sample Program ************************************************************************** // SuperIO relative definition (Please reference to Table 2) #define SIOIndex 0x2E #define SIOData 0x2F #define DIOLDN 0x06 IOWriteByte(byte IOPort, byte Value); IOReadByte(byte IOPort); // DIO relative definition (Please reference to Table 3) #define DirReg 0xA0 // 0:input, 1: output #define InputPin...
  • Page 128 // Input : Example, Set Digital I/O Pin 2 to high level AaeonSetOutputLevel(Pin2Bit, PinHigh); ************************************************************************** ************************************************************************** Boolean AaeonReadPinStatus(byte PinBit){ Boolean PinStatus ; PinStatus = SIOBitRead(DIOLDN, StatusReg, PinBit); Return PinStatus ; VOID AaeonSetOutputLevel(byte PinBit, byte Value){ ConfigDioMode(PinBit, OutputPin); SIOBitSet(DIOLDN, OutputReg, PinBit, Value); ******************************************************************************** ********************************************************************************VOID SIOEnterMBPnPMode(){...
  • Page 129 IOWriteByte(SIOData, TmpValue); SIOExitMBPnPMode(); VOID SIOByteSet(byte LDN, byte Register, byte Value){ SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); IOWriteByte(SIOData, Value); SIOExitMBPnPMode(); ******************************************************************************** ******************************************************************************** Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode();...

  • Page 130: Appendix E - Mating Connectors And Cables

    Appendix E Appendix E – Mating Connectors and Cables...

  • Page 131: Mating Connectors And Cables

    Mating Connectors and Cables Mating Connector Connector Available Cable Function Label Cable Vendor Model no External RTC Battery Molex 51021-0200 175011901C Connector Cable LVDS HIROSE DF13-30DS-1.25C Connector LVDS Inverter PHR-5 Connector SATA SATA CN14 Molex 88750-5318 1709070500 Connector Cable 2 Pins +5Vout CN15 PHR-2...
  • Page 132 +9~36V Vin Power CN30 1702002010 Connector Cable External Catch +5VSB Power CN32 Electron 2418HJ-06 output and PS_ON# External +5VSB Power CN33 PHR-3 170220020B Input and Cable PS_ON# CPU Fan CN36 Molex 22-01-2035 Connector Appendix E – Mating Connectors and Cables...

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