Operation; Table 2. Front Panel Description; Table 3. Dce Pin Assignments - ADTRAN Total Access 1500 SCU Installation And Maintenance Manual

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3. This constitutes a complete and successful
power-on test.
NOTE
Once successfully powered up, if only A or B
power is supplied, the SCU will reflect a MIN
alarm for A (or B) power failure.

3. OPERATION

Power
The Total Access backplane delivers two -48 VDC
buses to the SCU. The SCU operates with both or
either -48 VDC buses active.
Front Panel Indicators
See Table 2 for a description of front panel LEDs and
buttons.
User Interface
Since the SCU is the user access point to the shelf and
its access modules, it must support a number of user
physical interfaces and service the shelf's
communication buses. The SCU supports a craft port,
X.25 port, and an Ethernet port.
SCU COT
1180008L2
A
T
D
E
M
S
I
T
N
MJR
HST
MNR
MLT
BSY
RMT
ACO
61180008L1-5B

Table 2. Front Panel Description

L
E
D
C
l o
r o
M
J
R
O
f f
R
d e
M
N
R
O
f f
Y
l e
o l
w
R
M
T
O
f f
Y
l e
o l
w
A
C
O
O
f f
G
e r
n e
H
S
T
O
f f
G
e r
n e
M
L
T
B
S
Y
O
f f
G
e r
n e
S
w
t i
h c
A
C
O
P
e r
s s
o t
d
s i
S
w
t i
h c
e r
m
a
n i
a
t c
v i
Section 61180008L1-5, Issue 2
Craft Port
The SCU provides an RS-232 serial asynchronous
craft access port. Physical access is attained by
connecting a male-ended DB-9 cable to the female
DB-9 connector on the SCU front panel. This port can
operate at various baud rates and is limited to 8-bit
asynchronous data with no parity, one stop bit.
Minimal 3-wire functionality (pins 2, 3, and 5) is also
accommodated. This port operates as a DCE; pin
assignments are detailed in Table 3.

Table 3. DCE Pin Assignments

P
n i
N
u
m
b
r e
2
3
4
5
X.25 Port
The SCU supports synchronous RS-232 compatible
serial interface to be used in conjunction with an X.25
network. The unit includes PAD functions onboard so
an external PAD is not required for operation with the
X.25 network. Physical access uses a 25-pin female
DB-25 connector (J34) on the rear of the Total Access
1500 shelf. The X.25 connector pin assignments are
detailed in Table 4.
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