Sleepclk (Digital); Sleepclk (Analog) - Nokia NPD-1 Series Troubleshooting - Bb

NPD-1
Troubleshooting — BB
The system clock is stopped during sleep mode by disabling the VCTCXO power supply
(VR3) from the UEM regulator output by turning off the controlled output signal SleepX
from UPP.

SLEEPClk (Digital)

The UEM provides a 32kHz sleep clock for internal use and to UPP, where it is used for
the sleep mode timing. (See next figure.)

SLEEPClk (Analog)

When the system enters sleep mode or power off mode, the external 32KHz crystal pro-
vides a reference to the UEM RTC circuit to turn on the phone during power off or sleep
mode. (See next figure.)
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Figure 11: 32kHz Digital output from UEM
Nokia Corporation
CCS Technical Documentation
Confidential Issue 1 11/2002