Winbond W632GG6KB Series Manual
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Winbond W632GG6KB Series Manual

16m 8 banks 16 bit ddr3 sdram
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Table of Contents-

1.
GENERAL DESCRIPTION ................................................................................................................... 5
2.
FEATURES ........................................................................................................................................... 5
3.
ORDER INFORMATION ....................................................................................................................... 6
4.
KEY PARAMETERS ............................................................................................................................. 7
5.
BALL CONFIGURATION ...................................................................................................................... 8
6.
BALL DESCRIPTION ............................................................................................................................ 9
7.
BLOCK DIAGRAM .............................................................................................................................. 11
8.
FUNCTIONAL DESCRIPTION ............................................................................................................ 12
8.1
Basic Functionality .............................................................................................................................. 12
8.2
RESET and Initialization Procedure .................................................................................................... 12
8.2.1
Power-up Initialization Sequence ..................................................................................... 12
8.2.2
Reset Initialization with Stable Power .............................................................................. 14
8.3
Programming the Mode Registers ....................................................................................................... 15
8.3.1
Mode Register MR0 ......................................................................................................... 17
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.4
8.3.1.5
8.3.1.6
8.3.2
Mode Register MR1 ......................................................................................................... 20
8.3.2.1
8.3.2.2
8.3.2.3
8.3.2.4
8.3.2.5
8.3.2.6
8.3.3
Mode Register MR2 ......................................................................................................... 22
8.3.3.1
8.3.3.2
8.3.3.3
8.3.3.4
8.3.4
Mode Register MR3 ......................................................................................................... 24
8.3.4.1
8.4
No OPeration (NOP) Command .......................................................................................................... 25
8.5
Deselect Command ............................................................................................................................. 25
8.6
DLL-off Mode ...................................................................................................................................... 25
8.7
DLL on/off switching procedure ........................................................................................................... 26
DLL "on" to DLL "off" Procedure ....................................................................................... 26
8.7.1
DLL "off" to DLL "on" Procedure ....................................................................................... 27
8.7.2
8.8
Input clock frequency change ............................................................................................................. 28
8.8.1
Frequency change during Self-Refresh............................................................................ 28
8.8.2
Frequency change during Precharge Power-down .......................................................... 28
8.9
Write Leveling ..................................................................................................................................... 30
8.9.1
16M  8 BANKS  16 BIT DDR3 SDRAM
Burst Length, Type and Order ................................................................................ 18
CAS Latency........................................................................................................... 18
Test Mode............................................................................................................... 19
DLL Reset............................................................................................................... 19
Write Recovery ....................................................................................................... 19
Precharge PD DLL ................................................................................................. 19
DLL Enable/Disable ................................................................................................ 20
Output Driver Impedance Control ........................................................................... 21
ODT RTT Values .................................................................................................... 21
Additive Latency (AL) ............................................................................................. 21
Write leveling .......................................................................................................... 21
Output Disable ........................................................................................................ 21
Partial Array Self Refresh (PASR) .......................................................................... 23
CAS Write Latency (CWL) ...................................................................................... 23
Dynamic ODT (Rtt_WR) ......................................................................................... 23
Multi Purpose Register (MPR) ................................................................................ 24
- 1 -
W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06

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  • Page 1: Table Of Contents

    W632GG6KB 16M  8 BANKS  16 BIT DDR3 SDRAM Table of Contents- GENERAL DESCRIPTION ........................5 FEATURES ............................5 ORDER INFORMATION ........................6 KEY PARAMETERS ..........................7 BALL CONFIGURATION ........................8 BALL DESCRIPTION ..........................9 BLOCK DIAGRAM ..........................11 FUNCTIONAL DESCRIPTION ......................
  • Page 2 W632GG6KB 8.9.2 Write Leveling Procedure ....................31 8.9.3 Write Leveling Mode Exit ....................33 8.10 Multi Purpose Register ........................34 8.10.1 MPR Functional Description ..................... 35 8.10.2 MPR Register Address Definition ..................36 8.10.3 Relevant Timing Parameters .................... 36 8.10.4 Protocol Example ......................
  • Page 3 W632GG6KB 8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions .......... 89 8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry .. 89 8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit..92 8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods OPERATION MODE ...........................
  • Page 4 W632GG6KB 10.15.4 Speed Bin General Notes ....................137 10.16 AC Characteristics ........................138 10.16.1 AC Timing and Operating Condition for -11 speed grade ..........138 10.16.2 AC Timing and Operating Condition for -12/12I/-15/15I speed grades ......142 10.16.3 Timing Parameter Notes ....................146 10.16.4 Address / Command Setup, Hold and Derating .............

  • Page 5: General Description

    W632GG6KB 1. GENERAL DESCRIPTION The W632GG6KB is a 2G bits DDR3 SDRAM, organized as 16,777,216 words  8 banks  16 bits. This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various applications. The W632GG6KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I. The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification.

  • Page 6: Order Information

    W632GG6KB System level timing calibration support via write leveling and MPR read pattern  ZQ Calibration for output driver and ODT using external reference resistor to ground  Asynchronous RESET# pin for Power-up initialization sequence and reset function  Programmable on-die termination (ODT) for data, data mask and differential strobe pairs ...

  • Page 7: Key Parameters

    W632GG6KB 4. KEY PARAMETERS Speed Bin DDR3-1866 DDR3-1600 DDR3-1333 CL-nRCD-nRP 13-13-13 11-11-11 9-9-9 Unit Part Number Extension -12/12I -15/15I Parameter Sym. Min. Max. Min. Max. Min. Max. Maximum operating frequency using maximum    CKMAX allowed settings for Sup_CL and Sup_CWL 13.75 13.5 Internal read command to first data...

  • Page 8: Ball Configuration

    W632GG6KB 5. BALL CONFIGURATION DQU5 DQU7 DQU4 VDDQ VDDQ VSSQ DQSU# VSSQ DQU6 DQU1 VDDQ DQU3 DQSU DQU2 VDDQ VSSQ VDDQ DQU0 VSSQ VSSQ DQL0 VSSQ VDDQ VDDQ DQL2 DQSL DQL1 DQL3 VSSQ VSSQ DQL6 DQSL# VSSQ VREFDQ VDDQ DQL4 DQL5 VDDQ DQL7...

  • Page 9: Ball Description

    W632GG6KB 6. BALL DESCRIPTION BALL NUMBER SYMBOL TYPE DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and J7, K7 CK, CK# Input control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.
  • Page 10 W632GG6KB E3, F7, F2, F8, H3, DQL0−DQL7 Input/Output Data Input/Output: Lower byte of Bi-directional data bus. H8, G2, H7 D7, C3, C8, C2, A7, DQU0−DQU7 Input/Output Data Input/Output: Upper byte of Bi-directional data bus. A2, B8, A3 Lower byte data Strobe: Data Strobe output with read data, input with write data of DQL[7:0].

  • Page 11: Block Diagram

    W632GG6KB 7. BLOCK DIAGRAM CK, CK# CLOCK BUFFER CONTROL SIGNAL GENERATOR RAS# COMMAND DECODER CAS# COLUMN COLUMN COLUMN COLUMN DECODER DECODER DECODER DECODER CELL ARRAY CELL ARRAY CELL ARRAY CELL ARRAY BANK #5 BANK #0 BANK #1 BANK #4 MODE SENSE SENSE REGISTER...

  • Page 12: Functional Description

    W632GG6KB 8. FUNCTIONAL DESCRIPTION Basic Functionality The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
  • Page 13 W632GG6KB 4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until t before CKE is registered HIGH.

  • Page 14: Reset Initialization With Stable Power

    W632GG6KB 8.2.2 Reset Initialization with Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2 * V anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100 nS. CKE is pulled “LOW” before RESET being de-asserted (min.

  • Page 15: Programming The Mode Registers

    W632GG6KB Programming the Mode Registers For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation.
  • Page 16 W632GG6KB The MRS command to Non-MRS command delay, t is required for the DRAM to update the features, except DLL reset, and is the minimum time required from a MRS command to a non-MRS command excluding NOP and DES shown in Figure 4. Command VALID VALID...

  • Page 17: Mode Register Mr0

    W632GG6KB 8.3.1 Mode Register MR0 The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power Down, which include various vendor specific options to make DDR3 SDRAM useful for various applications.

  • Page 18: Burst Length, Type And Order

    W632GG6KB 8.3.1.1 Burst Length, Type and Order Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in Table 1.

  • Page 19: Test Mode

    W632GG6KB 8.3.1.3 Test Mode The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values shown in Figure 5. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM Manufacturer and should NOT be used.

  • Page 20: Mode Register Mr1

    W632GG6KB 8.3.2 Mode Register MR1 The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom impedance, additive latency, Write leveling enable and Qoff. The Mode Register 1 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to the Figure 6 below.

  • Page 21: Output Driver Impedance Control

    W632GG6KB The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally. 8.3.2.2 Output Driver Impedance Control The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in Figure 6.

  • Page 22: Mode Register Mr2

    W632GG6KB 8.3.3 Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the Figure 7 below.

  • Page 23: Partial Array Self Refresh (Pasr)

    W632GG6KB 8.3.3.1 Partial Array Self Refresh (PASR) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range shown in Figure 7 will be lost if Self Refresh is entered. Data integrity will be maintained if t conditions are met and no Self Refresh command is issued.

  • Page 24: Mode Register Mr3

    W632GG6KB 8.3.4 Mode Register MR3 The Mode Register MR3 controls Multi purpose registers. The Mode Register 3 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the Figure 8 below.

  • Page 25: No Operation (Nop) Command

    W632GG6KB No OPeration (NOP) Command The No OPeration (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP (CS# LOW and RAS#, CAS#, and WE# HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Deselect Command The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR3 SDRAM.

  • Page 26: Dll On/Off Switching Procedure

    W632GG6KB DLL on/off switching procedure DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit is set back to “0”. DLL “on” to DLL “off” Procedure 8.7.1 To switch from DLL “on”...

  • Page 27: Dll "Off" To Dll "On" Procedure

    W632GG6KB DLL “off” to DLL “on” Procedure 8.7.2 To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh: 1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (R ) must be in high impedance state before Self-Refresh mode is entered.) 2.

  • Page 28: Input Clock Frequency Change

    W632GG6KB Input clock frequency change Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of normal operation. This means that, once the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specifications.
  • Page 29 W632GG6KB Previous clock frequency New clock frequency CKSRE CKSRX CPDED Command VALID Address DLL Reset VALID AOFPD DQS, DQS# High-Z High-Z DLLK Exit PRECHARGE Enter PRECHARGE Frequency Power-Down Mode Change Power-Down Mode TIME BREAK DON'T CARE Notes: 1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down. 2.

  • Page 30: Write Leveling

    W632GG6KB Write Leveling For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on the DIMM.

  • Page 31: Dram Setting For Write Leveling & Dram Termination Function In That Mode

    W632GG6KB 8.9.1 DRAM setting for write leveling & DRAM termination function in that mode DRAM enters into Write leveling mode if A7 in MR1 set ‘High’ and after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set ‘Low’ (Table 3). Note that in write leveling mode, only DQS/DQS# terminations are activated and deactivated via ODT pin, unlike normal operation (Table 4).
  • Page 32 W632GG6KB Command WLDQSEN DQSL DQSH DQSL DQSH Diff_DQS One Prime DQ: WLMRD Prime DQ Late Remaining DQs Early Remaining DQs WLOE All DQs are Prime: WLMRD Late Prime DQs WLOE Early Prime DQs WLOE UNDEFINED DRIVING MODE DON'T CARE TIME BREAK Notes: 1.

  • Page 33: Write Leveling Mode Exit

    W632GG6KB 8.9.3 Write Leveling Mode Exit The following sequence describes how the Write Leveling Mode should be exited: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until t after the respective MR command (Te1).

  • Page 34: Multi Purpose Register

    W632GG6KB 8.10 Multi Purpose Register The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The basic concept of the MPR is shown in Figure 16. Memory Core (all banks precharged) MR3 [A2] Multipurpose register Pre-defined data for Reads DQ, DM, DQS, DQS#...

  • Page 35: Mpr Functional Description

    W632GG6KB 8.10.1 MPR Functional Description One bit wide logical interface via all DQ pins during READ operation.  Register Read:  — DQL[0] and DQU[0] drive information from MPR. — DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b. Addressing during for Multi Purpose Register reads for all MPR agents: ...

  • Page 36: Mpr Register Address Definition

    W632GG6KB 8.10.2 MPR Register Address Definition Table 6 provides an overview of the available data locations, how they are addressed by MR3 A[1:0] during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
  • Page 37 W632GG6KB Read:  A[1:0] = ‘00’b (Data burst order is fixed starting at nibble, always 00b here) A[2] = ‘0’b (For BL=8, burst order is fixed as 0,1,2,3,4,5,6,7) A12/BC# = 1 (use regular burst length of 8) All other address pins (including BA[2:0] and A10/AP): don't care After RL = AL + CL, DRAM bursts out the pre-defined Read Calibration Pattern.
  • Page 38 W632GG6KB Command PREA READ VALID MPRR VALID A[1:0] VALID A[2] A[9:3] VALID A10/AP VALID A[11] VALID A12/BC# VALID DQS, DQS# 1. RD with BL8 either by MRS or on the fly. TIME BREAK DON'T CARE NOTES: 2. Memory Controller must drive 0 on A[2:0]. Figure 17 –...
  • Page 39 W632GG6KB Command PREA READ READ VALID MPRR VALID VALID A[1:0] VALID A[2] A[9:3] VALID VALID A10/AP VALID VALID A[11] VALID VALID A12/BC# VALID VALID DQS, DQS# 1. RD with BL8 either by MRS or on the fly. TIME BREAK DON'T CARE NOTES: 2.
  • Page 40 W632GG6KB Command PREA READ READ VALID MPRR VALID VALID A[1:0] VALID A[2] A[9:3] VALID VALID A10/AP VALID VALID A[11] VALID VALID A12/BC# VALID VALID DQS, DQS# TIME BREAK DON'T CARE 1. RD with BC4 either by MRS or on the fly. NOTES: 2.
  • Page 41 W632GG6KB Command PREA READ READ VALID MPRR VALID VALID A[1:0] VALID A[2] A[9:3] VALID VALID A10/AP VALID VALID A[11] VALID VALID A12/BC# VALID VALID DQS, DQS# TIME BREAK DON'T CARE 1. RD with BC4 either by MRS or on the fly. NOTES: 2.

  • Page 42: Active Command

    W632GG6KB 8.11 ACTIVE Command The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0- A13 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank.

  • Page 43: Read Operation

    W632GG6KB 8.13 READ Operation 8.13.1 READ Burst Operation During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled). A12 = 0, BC4 (BC4 = burst chop, t = 4) A12 = 1, BL8 A12 is used only for burst length control, not as a column address.

  • Page 44: Read Timing Definitions

    W632GG6KB 8.13.2 READ Timing Definitions Read timing is shown in Figure 23 and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: min/max describes the allowed range for a rising data strobe edge relative to CK, CK#. DQSCK ...

  • Page 45: Read Timing; Clock To Data Strobe Relationship

    W632GG6KB 8.13.2.1 READ Timing; Clock to Data Strobe relationship Clock to Data Strobe relationship is shown in Figure 24 and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: min/max describes the allowed range for a rising data strobe edge relative to CK, CK#. DQSCK ...

  • Page 46: Read Timing; Data Strobe To Data Relationship

    W632GG6KB 8.13.2.2 READ Timing; Data Strobe to Data relationship The Data Strobe to Data relationship is shown in Figure 25 and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: describes the latest valid transition of the associated DQ pins. DQSQ ...

  • Page 47: Tlz(Dqs), Tlz(Dq), Thz(Dqs), Thz(Dq) Calculation

    W632GG6KB 8.13.2.3 t Calculation LZ(DQS) LZ(DQ) HZ(DQS) HZ(DQ) and t transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving t HZ(DQS) and t , or begins driving t...

  • Page 48: Trpre Calculation

    W632GG6KB 8.13.2.4 t Calculation RPRE The method for calculating differential pulse widths for t is shown in Figure 27. RPRE Single ended signal, provided as background information DQS# Single ended signal, provided as background information _begin RPRE RPRE DQS - DQS# Resulting differential signal, relevant for t specification...
  • Page 49 W632GG6KB Command READ READ Bank Bank Address Col n Col b RPST RPRE DQS, DQS# Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout RL = 6 RL = 6 NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0). 2.
  • Page 50 W632GG6KB Command READ READ Bank Bank Address Col n Col b RPST RPRE RPST RPRE DQS, DQS# Dout Dout Dout Dout Dout Dout Dout Dout RL = 6 RL = 6 NOTES: 1. BC4, RL = 6 (CL = 6, AL = 0) 2.
  • Page 51 W632GG6KB Command READ WRITE 4 clocks READ to WRITE Command Delay = RL + t / 2 + 2t - WL Bank Bank Address Col n Col b RPST WPRE WPST RPRE DQS, DQS# Dout Dout Dout Dout RL = 6 WL = 5 NOTES: 1.
  • Page 52 W632GG6KB Command READ READ Bank Address Bank Col b Col n RPRE RPST RPST RPRE DQS, DQS# Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout RL = 6 RL = 6 NOTES: 1. RL = 6 (CL = 6, AL = 0) 2.
  • Page 53 W632GG6KB Command READ READ WRITE 4 clocks READ to WRITE Command Delay = RL + t + 2t - WL Bank Bank Address Col n Col b WPST RPRE RPST WPRE DQS, DQS# Dout Dout Dout Dout Dout Dout Dout Dout RL = 6 WL = 5...

  • Page 54: Burst Read Operation Followed By A Precharge

    W632GG6KB 8.13.2.6 Burst Read Operation followed by a Precharge The minimum external Read command to Precharge command spacing to the same bank is equal to AL + t with t being the Internal Read Command to Precharge Command Delay. Note that the minimum ACT to PRE timing, t must be satisfied as well.
  • Page 55 W632GG6KB Command READ Bank a, Bank a, Bank a, Address (or all) Col n Row b AL = CL - 2 = 9 CL = 11 RL = 20 BL4 Operation: DQS, DQS# Dout Dout Dout Dout BL8 Operation: DQS, DQS# Dout Dout Dout...

  • Page 56: Write Operation

    W632GG6KB 8.14 WRITE Operation 8.14.1 DDR3 Burst Operation During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled). A12 = 0, BC4 (BC4 = burst chop, t = 4) A12 = 1, BL8 A12 is used only for burst length control, not as a column address.

  • Page 57: Write Data Mask

    W632GG6KB Command WRITE WL = AL + CWL Bank Address Col n DQSS WPST(min) WPRE(min) (min) DQSS DQS, DQS# DQSH(min) DQSL DQSH DQSL DQSH DQSL DQSH DQSL DQSH DQSL(min) WPST(min) WPRE(min) (nominal) DQSS DQS, DQS# DQSL DQSH(min) DQSH DQSL DQSH DQSL DQSH DQSL...

  • Page 58: Twpre Calculation

    W632GG6KB 8.14.4 t Calculation WPRE The method for calculating differential pulse widths for t is shown in Figure 41. WPRE _begin WPRE DQS - DQS# WPRE Resulting differential signal, relevant for t specification WPRE _end WPRE Figure 41 – Method for calculating t transitions and endpoints WPRE 8.14.5 t...
  • Page 59 W632GG6KB Command WRITE WL = AL + CWL Bank Address Col n WPST WPRE DQS, DQS# TRANSITIONING DATA DON'T CARE Notes: 1. BL8, WL = 5; AL = 0, CWL = 5. 2. Din n = data-in from column n. 3.
  • Page 60 W632GG6KB Command WRITE READ Bank Bank Address Col n Col b WPRE WPST DQS, DQS# WL = 5 RL = 6 TIME BREAK TRANSITIONING DATA DON'T CARE Notes: 1. BC4, WL = 5, RL = 6. 2. Din n = data-in from column n; Dout b = data-out from column b. 3.
  • Page 61 W632GG6KB WRITE Command 4 clocks Bank Address VALID Col n WPRE WPST DQS, DQS# WL = 5 NOTES: 1. BC4 on the fly, WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n. 3.
  • Page 62 W632GG6KB Command WRITE WRITE 4 clocks Bank Bank Address Col b Col n WPRE WPST WPRE WPST DQS, DQS# WL = 5 WL = 5 NOTES: 1. BC4, WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3.
  • Page 63 W632GG6KB Command WRITE READ 4 clocks Bank Bank Address Col n Col b WPST WPRE DQS, DQS# WL = 5 RL = 6 NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0) 2.
  • Page 64 W632GG6KB Command WRITE WRITE 4 clocks Bank Bank Address Col n Col b WPRE WPST DQS, DQS# WL = 5 WL = 5 NOTES: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3.

  • Page 65: Refresh Command

    W632GG6KB 8.15 Refresh Command The Refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command is non persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires Refresh cycles at an average periodic interval of t .
  • Page 66 W632GG6KB REFI 9 x t REFI 8 REF-Commands pulled-in Figure 56 – Postponing Refresh Commands (Example) REFI 9 x t REFI 8 REF-Commands pulled-in Figure 57 – Pulling-in Refresh Commands (Example) Publication Release Date: Jan. 03, 2017 Revision: A06 - 66 -...

  • Page 67: Self-Refresh Operation

    W632GG6KB 8.16 Self-Refresh Operation The Self-Refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM device has a built-in timer to accommodate Self-Refresh operation.
  • Page 68 W632GG6KB The use of Self-Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3 SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh Mode.

  • Page 69: Power-Down Modes

    W632GG6KB 8.17 Power-Down Modes 8.17.1 Power-Down Entry and Exit Power-down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read / write operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-precharge and refresh are in progress, but power-down I spec will not be applied until finishing those operations.
  • Page 70 W632GG6KB Command VALID VALID VALID VALID Address VALID VALID CPDED Enter Exit Power-Down Power-Down Mode Mode TIME BREAK DON'T CARE Note: 1. VALID command at T0 is ACT, NOP, DES or PRE with still one bank remaining open after completion of the precharge command.
  • Page 71 W632GG6KB Command WRITE VALID CPDED VALID Bank Address VALID Col n WL = AL + CWL DQS, DQS# DQ BL8 Start Internal Precharge DQ BC4 WRAPDEN Power-Down Entery TIME BREAK TRANSITIONING DATA DON'T CARE Note: 1. t is programmed through MR0. Figure 61 –...
  • Page 72 W632GG6KB Command VALID VALID CPDED VALID VALID Enter Exit Power-Down Power-Down Mode Mode TIME BREAK DON'T CARE Figure 63 – Precharge Power-Down (Fast Exit Mode) Entry and Exit Command VALID VALID VALID CPDED VALID VALID VALID XPDLL Enter Exit Power-Down Power-Down Mode Mode...
  • Page 73 W632GG6KB Command VALID VALID Address VALID VALID VALID CPDED VALID REFPDEN TIME BREAK DON'T CARE Figure 65 – Refresh Command to Power-Down Entry Command VALID ACTIVE VALID Address VALID VALID VALID CPDED VALID ACTPDEN TIME BREAK DON'T CARE Figure 66 – Active Command to Power-Down Entry Publication Release Date: Jan.
  • Page 74 W632GG6KB PRE or Command VALID VALID PREA Address VALID VALID VALID CPDED VALID PREPDEN TIME BREAK DON'T CARE Figure 67 – Precharge / Precharge all Command to Power-Down Entry Command VALID Address VALID VALID CPDED VALID MRSPDEN DON'T CARE TIME BREAK Figure 68 –...

  • Page 75: Power-Down Clarifications - Case 1

    W632GG6KB 8.17.2 Power-Down clarifications - Case 1 When CKE is registered low for power-down entry, t (min) must be satisfied before CKE can be registered high for power-down exit. The minimum value of parameter t (min) is equal to the (min) as shown in section 10.16 “AC Characteristics”...

  • Page 76: Power-Down Clarifications - Case 3

    W632GG6KB 8.17.4 Power-Down clarifications - Case 3 If an early PD Entry is issued after a Refresh command, once PD Exit is issued, NOP or DES with CKE High must be issued until t (min) from the Refresh command is satisfied. This means CKE can not be registered low twice within a t (min) window.

  • Page 77: Zq Calibration Commands

    W632GG6KB 8.18 ZQ Calibration Commands 8.18.1 ZQ Calibration Description ZQ Calibration command is used to calibrate DRAM R & ODT values over PVT (process, voltage and temperature). An external resistor (R ) between the DRAM ZQ pin and ground is used as a calibration reference.

  • Page 78: Zq Calibration Timing

    W632GG6KB 8.18.2 ZQ Calibration Timing Command ZQCL VALID VALID ZQCS VALID Address VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID DQ Bus Hi-Z ACTIVITIES ACTIVITIES Hi-Z ZQCS ZQinit or ZQoper DON'T CARE TIME BREAK Notes: 1. CKE must be continuously registered high during the calibration procedure. 2.

  • Page 79: On-Die Termination (Odt)

    W632GG6KB 8.19 On-Die Termination (ODT) ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each DQU, DQL, DQSU, DQSU#, DQSL, DQSL#, DMU and DML signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.

  • Page 80: Synchronous Odt Mode

    W632GG6KB 8.19.2 Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power- down definition, these modes are: Any bank active with CKE high  Refresh with CKE high  Idle mode with CKE high ...
  • Page 81 W632GG6KB AL = 3 AL = 3 CWL - 2 ODTH4min ODTLoff = CWL + AL - 2 ODTLon = CWL + AL - 2 AOFmin AONmin DRAM_RTT Rtt_Nom AONmax AOFmax TRANSITIONING DON'T CARE Figure 74 – Synchronous ODT Timing (AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6) Command WRS4 ODTH4...

  • Page 82: Odt During Reads

    W632GG6KB 8.19.2.3 ODT during Reads As the DDR3 SDRAM can not terminate and drive at the same time, R must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. R may not be enabled until the end of the post-amble as shown in the example below.

  • Page 83: Dynamic Odt

    W632GG6KB 8.19.3 Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by the “Dynamic ODT” feature as described as follows: 8.19.3.1 Functional Description: The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’.

  • Page 84: Odt Timing Diagrams

    W632GG6KB Table 10 – Latencies and timing parameters relevant for Dynamic ODT Definition for all DDR3 Name and Description Abbr. Defined from Defined to Unit speed bins Registering external ODT turn-on Latency ODTLon Turning termination on ODTLon = WL - 2 ODT signal high Registering external ODT turn-off Latency...
  • Page 85 W632GG6KB WRS4 Address VALID ODTH4 ODTLoff ODTH4 ODTLon ODTLcwn4 ADCmin ADCmin AOFmin AONmin Rtt_Nom Rtt_WR Rtt_Nom AONmax ODTLcnw ADCmax ADCmax AOFmax DQS, DQS# TRANSITIONING DON'T CARE NOTES: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command. In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
  • Page 86 W632GG6KB Command VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID Address ODTH4 ODTLon ODTLoff AONmin AOFmin Rtt_Nom AONmax AOFmax DQS, DQS# TRANSITIONING DON'T CARE Notes: 1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied. 2.
  • Page 87 W632GG6KB ODTLcnw Command WRS4 Address VALID ODTH4 ODTLoff ODTLon AONmin ADCmin AOFmin Rtt_WR Rtt_Nom ADCmax ODTLcwn4 ADCmax AOFmax DQS, DQS# TRANSITIONING DON'T CARE Notes: 1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied. 2.

  • Page 88: Asynchronous Odt Mode

    W632GG6KB 8.19.4 Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL is disabled during precharge power down by MR0 bit A12.

  • Page 89: Synchronous To Asynchronous Odt Mode Transitions

    W632GG6KB 8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions – Table 13 ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period Description Min. Max. min{ ODTLon * t min; t min } max{ ODTLon * t max;...
  • Page 90 W632GG6KB Command CPDED ANPD CPDEDmin PD entry transition period Last sync, ODT AOFmin ODTLoff AOFmax AOFPDmax ODTLoff + t AOFmin Sync or async, ODT AOFPDmin ODTLoff + t AOFmax First async, ODT AOFPDmin PD entry transition period AOFPDmax TRANSITIONING DATA DON'T CARE Figure 83 –...
  • Page 91 W632GG6KB Command (min) ANPD CPDED PD entry transition period Last sync, ODT AOFPD ODTLoff ODTLoff + t AOFPD Sync or async, ODT AOFPD ODTLoff + t AOFPD First async, ODT AOFPD AOFPD TIME BREAK TRANSITIONING DON'T CARE Figure 84 – Synchronous to asynchronous transition after Refresh command (AL = 0; CWL = 5; t = WL - 1 = 4) ANPD Publication Release Date: Jan.

  • Page 92: Asynchronous To Synchronous Odt Mode Transition During Power-Down Exit

    W632GG6KB 8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM.

  • Page 93: Asynchronous To Synchronous Odt Mode During Short Cke High And Short Cke Low Periods

    W632GG6KB 8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap (see Figure 86). In this case, the response of the DDR3 SDRAMs R to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period).

  • Page 94: Operation Mode

    W632GG6KB 9. OPERATION MODE Command Truth Table Notes 1, 2, 3 and 4 apply to the entire Command Truth Table. Note 5 Applies to all Read/Write commands. [BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don't Care, V=Valid] Table 14 – Command Truth Table BA0- A12/ A10/...
  • Page 95 W632GG6KB Notes: 1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA are device density and configuration dependent. 2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.

  • Page 96: Cke Truth Table

    W632GG6KB CKE Truth Table Notes 1-7 apply to the entire CKE Truth Table. For Power-down entry and exit parameters See 8.17 “Power-Down Modes” on page 69. CKE low is allowed only if t and t are satisfied. Table 15 – CKE Truth Table COMMAND (N) CURRENT ACTION (N)

  • Page 97: Simplified State Diagram

    W632GG6KB Simplified State Diagram This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. CKE_ L Power Applied...

  • Page 98: Electrical Characteristics

    W632GG6KB 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Voltage on V pin relative to V -0.4 ~ 1.975 1, 3 Voltage on V pin relative to V -0.4 ~ 1.975 1, 3 Voltage on any pin relative to V -0.4 ~ 1.975 Storage Temperature -55 ~ 150...

  • Page 99: Input And Output Leakage Currents

    W632GG6KB 10.4 Input and Output Leakage Currents SYMBOL PARAMETER MIN. MAX. UNIT NOTES Input Leakage Current µA (0V ≤ ≤ Output Leakage Current µA (Output disabled, 0V ≤ ≤ Notes: 1. All other balls not under test = 0 V. 2.

  • Page 100: Dc And Ac Input Measurement Levels

    W632GG6KB 10.6 DC and AC Input Measurement Levels 10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals Table 17 – Single-Ended DC and AC Input Levels for Command and Address DDR3-1333, DDR3-1600 DDR3-1866 PARAMETER SYMBOL UNIT NOTES MIN.

  • Page 101: Dc And Ac Input Levels For Single-Ended Data Signals

    W632GG6KB 10.6.2 DC and AC Input Levels for Single-Ended Data Signals Table 18 – Single-Ended DC and AC Input Levels for DQ and DM DDR3-1333, DDR3-1600 DDR3-1866 PARAMETER SYMBOL UNIT NOTES MIN. MAX. MIN. MAX. DC input logic high V + 0.100 + 0.100 IH.DQ(DC100)
  • Page 102 W632GG6KB The DC-tolerance limits and AC-noise limits for the reference voltages V and V REFCA REFDQ illustrated in Figure 89. It shows a valid reference voltage V (t) as a function of time. (V stands for V and V likewise). REFCA REFDQ is the linear average of V...

  • Page 103: Differential Swing Requirements For Clock (Ck - Ck#) And Strobe (Dqs - Dqs#)

    W632GG6KB 10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) Table 19 – Differential DC and AC Input Level DDR3-1333, DDR3-1600 & DDR3-1866 PARAMETER SYMBOL UNIT NOTES MIN. MAX. +0.200 Note 3 Differential input high IHDIFF Note 3 -0.200...

  • Page 104: Single-Ended Requirements For Differential Signals

    W632GG6KB Table 20 – Allowed time before ringback (t ) for CK - CK# and DQS - DQS# DVAC DDR3-1333/1600 DDR3-1866 [pS] [pS] [pS] [pS] DVAC DVAC DVAC DVAC Slew Rate IH/LDIFF(AC) IH/LDIFF(AC) IH/LDIFF(AC) IH/LDIFF(AC) [V/nS] 350mV 300mV 300mV (CK - CK#) only Min.

  • Page 105: Differential Input Cross Point Voltage

    W632GG6KB or V /2 or V CK or DQS or V time Figure 91 – Single-ended requirement for differential signals Note that, while ADD/CMD and DQ signal requirements are with respect to V , the single-ended components of differential signals have a requirement with respect to V /2;...

  • Page 106: Slew Rate Definitions For Single-Ended Input Signals

    W632GG6KB Table 22 – Cross point voltage for differential input signals (CK, DQS) DDR3-1333, DDR3-1600 & DDR3-1866 PARAMETER SYMBOL UNIT NOTES MIN. MAX. Differential Input Cross Point Voltage - 150 IX(CK) relative to V /2 for CK, CK# - 175 Differential Input Cross Point Voltage -150 IX(DQS)

  • Page 107: Dc And Ac Output Measurement Levels

    W632GG6KB 10.7 DC and AC Output Measurement Levels Table 24 – Single-ended DC and AC Output Levels PARAMETER SYMBOL VALUE UNIT NOTES DC output high measurement level (for IV curve linearity) 0.8 x V OH(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V OM(DC) DC output low measurement level (for IV curve linearity)

  • Page 108: Single Ended Output Slew Rate

    W632GG6KB 10.7.1.1 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V and V for single ended signals as shown in Table 27 OL(AC) OH(AC) and Figure 94.

  • Page 109: Differential Output Slew Rate

    W632GG6KB 10.7.1.2 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V and V for differential signals as shown in Table OL.DIFFAC) OH.DIFF(AC) 28 and Figure 95. Table 28 –...

  • Page 110: Ohm Output Driver Dc Electrical Characteristics

    W632GG6KB 10.8 34 ohm Output Driver DC Electrical Characteristics A functional representation of the output buffer is shown in Figure 96. Output driver impedance RON is selected by bits “D.I.C” A1 and A5 in the MR1 Register. Two different values can be selected via MR1 settings: / 7 (nominal 34.3 Ω...
  • Page 111 W632GG6KB Table 29 – Output Driver DC Electrical Characteristics, assuming RZQ = 240 Ω; entire operating temperature range; after proper ZQ calibration Resistor MIN. NOM. MAX. UNIT NOTES = 0.2 × V RZQ/7 1, 2, 3 OLDC = 0.5 × V RZQ/7 1, 2, 3 34Pd...

  • Page 112: Output Driver Temperature And Voltage Sensitivity

    W632GG6KB 10.8.1 Output Driver Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 30 and Table 31. ΔT = T - T(@calibration); ΔV= V (@calibration); V Note: dR dT and dR dV are not subject to production test but are verified by design and characterization.

  • Page 113: On-Die Termination (Odt) Levels And Characteristics

    W632GG6KB 10.9 On-Die Termination (ODT) Levels and Characteristics 10.9.1 ODT Levels and I-V Characteristics On-Die Termination effective resistance R is defined by bits A9, A6 and A2 of the MR1 Register. ODT is applied to the DQ, DM and DQS/DQS# pins. A functional representation of the on-die termination is shown in Figure 97.

  • Page 114: Odt Dc Electrical Characteristics

    W632GG6KB 10.9.2 ODT DC Electrical Characteristics and ΔV An overview about the specification requirements for R is provided in Table 32. Table 32 – ODT DC Impedance and Mid-Level Requirements MR1 A9, A6, A2 Resistor Min. Nom. Max. Unit Notes 120 Ω...

  • Page 115: Design Guide Lines For Rtt Pu And Rtt Pd

    W632GG6KB 10.9.4 Design guide lines for R and R Table 35 provides an overview of the ODT DC electrical pull-up and pull-down characteristics. The values are not specification requirements, but can be used as design guide lines. Table 35 – ODT DC Electrical Pull-Down and Pull-Up Characteristics, assuming R = 240 Ω...

  • Page 116: Odt Timing Definitions

    W632GG6KB 10.10 ODT Timing Definitions 10.10.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in Figure 98. VDDQ CK, CK# DQ, DM VTT = VSSQ DQS, DQS# RTT = 25Ω VSSQ Timing reference point Figure 98 –...
  • Page 117 W632GG6KB Begin point: Rising edge of CK – CK# defined by the end point of ODTL on DQ, DM DQS, DQS# End point: Extrapolated point at V Figure 99 – Definition of t Begin point: Rising edge of CK - CK# with ODT being first registered high AONPD DQ, DM...
  • Page 118 W632GG6KB Begin point: Rising edge of CK - CK# defined by the end point of ODTLoff End point: Extrapolated point at VRtt_Nom VRtt_Nom DQ, DM DQS, DQS# Figure 101 – Definition of t Begin point: Rising edge of CK – CK# with ODT being first registered low AOFPD End point: Extrapolated point at VRtt_Nom...
  • Page 119 W632GG6KB Begin point: Rising edge of CK – CK# Begin point: Rising edge of CK – CK# defined by defined by the end point of ODTLcnw the end point of ODTLcwn4 or ODTLcwn8 VRtt_Nom VRtt_Nom SW21 End point: Extrapolated point at VRtt_Nom DQ, DM DQS, DQS# VRtt_WR...

  • Page 120: Input/Output Capacitance

    W632GG6KB 10.11 Input/Output Capacitance DDR3-1333 DDR3-1600 DDR3-1866 PARAMETER SYMBOL UNIT NOTES MIN. MAX. MIN. MAX. MIN. MAX. Input/output capacitance 1, 2, 3 (DQ, DM, DQS, DQS#) Input capacitance 2, 3 (CK and CK#) Delta of input capacitance 0.15 0.15 0.15 2, 3, 4 (CK and CK#) Delta of Input/Output capacitance...

  • Page 121: Overshoot And Undershoot Specifications

    W632GG6KB 10.12 Overshoot and Undershoot Specifications 10.12.1 AC Overshoot /Undershoot Specification for Address and Control Pins: Applies to A0-A13, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT PARAMETER DDR3-1333 DDR3-1600 DDR3-1866 UNIT Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above V 0.33 0.28...

  • Page 122: Idd And Iddq Specification Parameters And Test Conditions

    W632GG6KB 10.13 I and I Specification Parameters and Test Conditions 10.13.1 I and I Measurement Conditions In this section, I and I measurement conditions such as test load and patterns are defined. Figure 105 shows the setup and test load for I and I measurements.
  • Page 123 W632GG6KB (optional) DDR3 RESET# SDRAM CK/CK# = 25 Ω DQS, DQS#, DQ, DM RAS#, CAS#, WE# A, BA NOTE: DIMM level Output test load condition may be different from above. Figure 105 – Measurement Setup and Test Load for I and I (optional) Measurements Application specific...
  • Page 124 W632GG6KB Table 39 – Basic and I Measurement Conditions SYM. DESCRIPTION Operating One Bank Active-Precharge Current CKE: High; External clock: On; t , nRC, nRAS, CL: see Table 38; BL: 8 ; AL: 0; CS#: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 40;...
  • Page 125 W632GG6KB Basic IDD and IDDQ Measurement Conditions, continued SYM. DESCRIPTION Operating Burst Read Current (1,6) CKE: High; External clock: On; t , CL: see Table 38; BL: 8 ; AL: 0; CS#: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 44; Data IO: DD4R seamless read data burst with different data between one burst and the next one according to Table 44;...
  • Page 126 W632GG6KB Table 40 – I Measurement-Loop Pattern Data 1, 2 D, D 3, 4 D#, D# Repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS Repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 1*nRC+1, 2 D, D 1*nRC+3, 4 D#, D#...
  • Page 127 W632GG6KB Table 41 – I Measurement-Loop Pattern Data 1, 2 D, D 3, 4 D#, D# Repeat pattern 1...4 until nRCD - 1, truncate if necessary nRCD 00000000 Repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS Repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 1*nRC+1, 2 D, D...
  • Page 128 W632GG6KB Table 42 – I and I Measurement-Loop Pattern DD2N DD3N Data Repeat Sub-Loop 0, use BA[2:0] = 1 instead 8-11 Repeat Sub-Loop 0, use BA[2:0] = 2 instead 12-15 Repeat Sub-Loop 0, use BA[2:0] = 3 instead 16-19 Repeat Sub-Loop 0, use BA[2:0] = 4 instead 20-23 Repeat Sub-Loop 0, use BA[2:0] = 5 instead 24-27...
  • Page 129 W632GG6KB Table 44 – I and I Measurement-Loop Pattern DD4R DDQ4R Data 00000000 2, 3 D#, D# 00110011 6, 7 D#, D# 8-15 Repeat Sub-Loop 0, but BA[2:0] = 1 16-23 Repeat Sub-Loop 0, but BA[2:0] = 2 24-31 Repeat Sub-Loop 0, but BA[2:0] = 3 32-39 Repeat Sub-Loop 0, but BA[2:0] = 4 40-47...
  • Page 130 W632GG6KB Table 46 – I Measurement-Loop Pattern DD5B Data 1, 2 D, D 3, 4 D#, D# 5...8 Repeat cycles 1...4, but BA[2:0] = 1 9...12 Repeat cycles 1...4, but BA[2:0] = 2 13...16 Repeat cycles 1...4, but BA[2:0] = 3 17...20 Repeat cycles 1...4, but BA[2:0] = 4 21...24...
  • Page 131 W632GG6KB Table 47 – I Measurement-Loop Pattern ATTENTION: Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Data 00000000 Repeat above D Command until nRRD - 1 nRRD nRRD+1 00110011 nRRD+2 Repeat above D Command until 2 * nRRD -1 Repeat Sub-Loop 0, but BA[2:0] = 2 2*nRRD 3*nRRD...

  • Page 132: Idd Current Specifications

    W632GG6KB 10.13.2 I Current Specifications Speed Bin DDR3-1333 DDR3-1600 DDR3-1866 SYM. Part Number Extension -15/15I -12/12I UNIT DEFINITION MAX. MAX. MAX. Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Standby Current DD2N Precharge Standby ODT Current DD2NT Precharge Power Down Current Slow Exit DD2P0 Precharge Power Down Current Fast Exit...

  • Page 133: Clock Specification

    W632GG6KB 10.14 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device. Definition for tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where CK(avg) each clock period is calculated from rising edge to rising edge.

  • Page 134: Speed Bins

    W632GG6KB Definition for tJIT(cc) and tJIT(cc,lck) is defined as the absolute difference in clock period between two consecutive clock cycles. JIT(cc) = Max of |{t i +1 - t i}|. JIT(cc) defines the cycle to cycle jitter when the DLL is already locked. JIT(cc) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

  • Page 135: Ddr3-1600 Speed Bin And Operating Conditions

    W632GG6KB 10.15.2 DDR3-1600 Speed Bin and Operating Conditions Speed Bin DDR3-1600 CL-nRCD-nRP 11-11-11 UNIT NOTES Part Number Extension -12/12I Parameter Symbol Min. Max. Maximum operating frequency using maximum  CKMAX allowed settings for Sup_CL and Sup_CWL Internal read command to first data 13.75 (13.125) * ...

  • Page 136: Ddr3-1866 Speed Bin And Operating Conditions

    W632GG6KB 10.15.3 DDR3-1866 Speed Bin and Operating Conditions Speed Bin DDR3-1866 CL-nRCD-nRP 13-13-13 UNIT NOTES Part Number Extension Parameter Symbol Min. Max. Maximum operating frequency using maximum  CKMAX allowed settings for Sup_CL and Sup_CWL Internal read command to first data 13.91 ...

  • Page 137: Speed Bin General Notes

    W632GG6KB 10.15.4 Speed Bin General Notes The absolute specification for all speed bins is T and V = 1.5V ± 0.075V. In addition OPER the following general notes apply. 1. Max. limits are exclusive. E.g. if t value is 2.5 nS, t needs to be <...

  • Page 138: Ac Characteristics

    W632GG6KB 10.16 AC Characteristics 10.16.1 AC Timing and Operating Condition for -11 speed grade SPEED GRADE DDR3-1866 (-11) SYMBOL UNITS NOTES PARAMETER MIN. MAX. Common Notes 1, 2, 3, 4 Clock Input Timing  -off) Minimum clock cycle time (DLL-off mode) See “Speed Bin”...
  • Page 139 W632GG6KB AC Timing and Operating Condition for -11 speed grade, continued SPEED GRADE DDR3-1866 (-11) SYMBOL UNITS NOTES PARAMETER MIN. MAX. Data Timing  DQS, DQS# to DQ skew, per group, per access DQSQ  DQ output hold time from DQS, DQS# 0.38 (avg) 18, 23...
  • Page 140 W632GG6KB AC Timing and Operating Condition for -11 speed grade, continued SPEED GRADE DDR3-1866 (-11) SYMBOL UNITS NOTES PARAMETER MIN. MAX. Command and Address Timing  DLL locking time DLLK Internal READ Command to PRECHARGE  max(4nCK, 7.5nS) Command delay Delay from start of internal write transaction to ...
  • Page 141 W632GG6KB AC Timing and Operating Condition for -11 speed grade, continued SPEED GRADE DDR3-1866 (-11) SYMBOL UNITS NOTES PARAMETER MIN. MAX. Power Down Timing Exit Power Down with DLL on to any valid  command; Exit Precharge Power Down with DLL max(3nCK, 6nS) frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to...

  • Page 142: Ac Timing And Operating Condition For -12/12I/-15/15I Speed Grades

    W632GG6KB 10.16.2 AC Timing and Operating Condition for -12/12I/-15/15I speed grades DDR3-1600 DDR3-1333 SPEED GRADE (-12/12I) (-15/15I) SYMBOL UNITS NOTES PARAMETER MIN. MAX. MIN. MAX. Common Notes 1, 2, 3, 4 Clock Input Timing   -off) Minimum clock cycle time (DLL-off mode) See “Speed Bin”...
  • Page 143 W632GG6KB AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued DDR3-1600 DDR3-1333 SPEED GRADE (-12/12I) (-15/15I) SYMBOL UNITS NOTES PARAMETER MIN. MAX. MIN. MAX. Data Timing   DQS, DQS# to DQ skew, per group, per access DQSQ  ...
  • Page 144 W632GG6KB AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued DDR3-1600 DDR3-1333 SPEED GRADE (-12/12I) (-15/15I) SYMBOL UNITS NOTES PARAMETER MIN. MAX. MIN. MAX. Command and Address Timing   WRITE recovery time 8, 26   Mode Register Set command cycle time max(12nCK, max(12nCK, ...
  • Page 145 W632GG6KB AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued DDR3-1600 DDR3-1333 SPEED GRADE (-12/12I) (-15/15I) SYMBOL UNITS NOTES PARAMETER MIN. MAX. MIN. MAX. Power Down Timing Exit Power Down with DLL on to any valid max(3nCK, max(3nCK,  ...

  • Page 146: Timing Parameter Notes

    W632GG6KB 10.16.3 Timing Parameter Notes 1. Unit ‘t avg)’ represents the actual t (avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. For example, t = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x t (avg) + (4per),min (which is smaller than 4 x t...
  • Page 147 W632GG6KB 17. When the device is operated with input clock jitter, this parameter needs to be derated by the actual (mper),act of the input clock, where 2 ≤ m ≤ 12. (output deratings are relative to the actual SDRAM input clock.) For example, if the measured jitter into a DDR3-1333 SDRAM has t (mper),act,min = - 138 pS and (mper),act,max = + 155 pS, then...
  • Page 148 W632GG6KB 33. One ZQCS command can effectively correct a minimum of 0.5 % (ZQ Correction) of RON and R impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables.

  • Page 149: Address / Command Setup, Hold And Derating

    W632GG6KB 10.16.4 Address / Command Setup, Hold and Derating For all input signals the total t (setup time) and t (hold time) required is calculated by adding the value (see Table 48) to the Δt and Δt datasheet t and t derating value (see Table 49 IS(base) IH(base)
  • Page 150 W632GG6KB Table 49 – Derating values DDR3-1333/1600 t - AC/DC based AC175 Threshold ΔtIS, ΔtIH derating in [pS] AC/DC based CMD/ AC175 Threshold -> VIH(AC)=VREF(DC)+175mV, VIL(AC)=VREF(DC)-175mV CK, CK# Differential Slew Rate Slew rate 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS...
  • Page 151 W632GG6KB Table 51 – Derating values DDR3-1866 t - AC/DC based Alternate AC135 Threshold ΔtIS, ΔtIH derating in [pS] AC/DC based CMD/ Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV CK, CK# Differential Slew Rate Slew rate 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS...
  • Page 152 W632GG6KB Note: Clock and Strobe are drawn on a different time scale. DQS# VDDQ IH(AC) to AC region IH(DC) nominal slew rate REF(DC) nominal slew rate IL(DC) to AC region IL(AC) ΔTF ΔTR – V min - V Setup Slew Rate Setup Slew Rate REF(DC) IL(AC)
  • Page 153 W632GG6KB Note: Clock and Strobe are drawn on a different time scale. DQS# IH(AC) IH(DC) DC to V nominal region slew rate REF(DC) nominal slew rate DC to V region IL(DC) IL(AC) ΔTR ΔTF – V min - V Hold Slew Rate REF(DC) IL(DC) Hold Slew Rate...
  • Page 154 W632GG6KB Note: Clock and Strobe are drawn on a different time scale. DQS# nominal line IH(AC) to AC region IH(DC) tangent line REF(DC) tangent line IL(DC) to AC region IL(AC) nominal line ΔTR tangent line [V min - V IH(AC) REF(DC) Setup Slew Rate ΔTF...
  • Page 155 W632GG6KB Note: Clock and Strobe are drawn on a different time scale. DQS# IH(AC) nominal line IH(DC) DC to V tangent region line REF(DC) tangent DC to V line nominal region line IL(DC) IL(AC) ΔTR ΔTF tangent line [V max] Hold Slew Rate REF(DC) IL(DC)

  • Page 156: Data Setup, Hold And Slew Rate Derating

    W632GG6KB 10.16.5 Data Setup, Hold and Slew Rate Derating For all input signals the total t (setup time) and t (hold time) required is calculated by adding the value (see Table 54) to the Δt and Δt data sheet t and t (see Table 55 and Table DS(base)
  • Page 157 W632GG6KB Table 55 – Derating values for DDR3-1333/1600 t - (AC150) ΔtDS, ΔtDH derating in [pS] AC/DC based DQS, DQS# Differential Slew Rate Slew rate 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS 1.0 V/nS (V/nS) ΔtDS ΔtDH...

  • Page 158: Package Specification

    W632GG6KB 11. PACKAGE SPECIFICATION Package Outline WBGA96 (9x13 mm , ball pitch: 0.8mm, Ø =0.45mm) Pin A1 index Pin A1 index 96xΦb THE WINDOW-SIDE SOLDER BALL DIAMETER REFERS. ENCAPSULANT TO POST REFLOW CONDITION. ddd M SEATING PLANE DIMENSION (MM) SYMBOL MIN.

  • Page 159: Revision History

    W632GG6KB 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION Feb. 18, 2013 Initial formally datasheet Revise storage temperature up to 150°C Revise -11 speed grade DDR3-1866 data setup/hold 138, 147, 155 time AC parameters t spec Revise all speed grades t min.

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