Table of Contents
Advertisement
X299 Taichi CLX
IO-L (D2)
Configure IO latency for channel B2.
ODT Setting
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.
ODT WR (A2)
Configure the memory on die termination resistors' WR for channel A2.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B1.
ODT WR (B2)
Configure the memory on die termination resistors' WR for channel B2.
ODT WR (C1)
Configure the memory on die termination resistors' WR for channel C1.
ODT WR (C2)
Configure the memory on die termination resistors' WR for channel C2.
ODT WR (D1)
Configure the memory on die termination resistors' WR for channel D1.
ODT WR (D2)
Configure the memory on die termination resistors' WR for channel D2.
ODT PARK (A1)
Configure the memory on die termination resistors' PARK for channel A1.
ODT PARK (A2)
Configure the memory on die termination resistors' PARK for channel A2.
ODT PARK (B1)
Configure the memory on die termination resistors' PARK for channel B1.
ODT PARK (B2)
Configure the memory on die termination resistors' PARK for channel B2.
81
Advertisement
Table of Contents
