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This user's guide describes the characteristics, operation, and use of the TPD1E04U04 EVM evaluation
module (EVM). This EVM includes six TPD1E04U04s in various configurations for testing. Five
TPD1E04U04s are configured for IEC 61000-4-2 compliance testing and one is configured for 2-port s-
parameter analysis. This user's guide includes setup instructions, schematic diagrams, a bill of materials,
and printed-circuit board layout drawings for the evaluation module.
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IEC 61000-4-2 Test Levels
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Bill of Materials
SLVUAN8 - April 2016
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Copyright © 2016, Texas Instruments Incorporated
TPD1E04U04 Evaluation Module
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User's Guide
SLVUAN8 - April 2016
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TPD1E04U04 Evaluation Module
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Table of Contents
Related Manuals for Texas Instruments TPD1E04U04
Summary of Contents for Texas Instruments TPD1E04U04
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Page 1: Table Of Contents
SLVUAN8 – April 2016 TPD1E04U04 Evaluation Module This user's guide describes the characteristics, operation, and use of the TPD1E04U04 EVM evaluation module (EVM). This EVM includes six TPD1E04U04s in various configurations for testing. Five TPD1E04U04s are configured for IEC 61000-4-2 compliance testing and one is configured for 2-port s- parameter analysis. -
Page 2: Introduction
TPD1E04U04 device. The TPD1E04U04 is a unidirectional TVS ESD protection diode for HDMI 2.0 and USB 3.0 high speed data line protection. The TPD1E04U04 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). -
Page 3: Setup
While the simulator is in direct contact with the test point during contact, it is not during air-gap. SLVUAN8 – April 2016 TPD1E04U04 Evaluation Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 4: Scattering Parameters
ESD. Scattering Parameters A TPD1E04U04 (D6) is configured with 2 SMA (J1 and J2) connectors to allow 2-port analysis with a vector network analyzer. Connect Port 1 to J1 and Port 2 to J2. This configuration allows for the following terminology in 2-port analysis: •... - Page 5 Recommended settings for the time axis is 20 ns/div and for the voltage axis is 10 V division. The voltage levels of the ESD applied to J1.Pin1 should not exceed ±8 kV while capturing clamping waveforms. SLVUAN8 – April 2016 TPD1E04U04 Evaluation Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated...
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Page 6: Board Layout
FR408HR at 0.062 inch thickness. Layers 2, 3, and 4 are ground planes and not shown here. Figure 3. TPD1E04U04EVM Top Layer and Silkscreen Schematics Figure 4. TPD1E04U04EVM Schematic TPD1E04U04 Evaluation Module SLVUAN8 – April 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... -
Page 7: Bill Of Materials
J1, J2 Connector, TH, End launch Connector, TH, 142-0761-881 Johnson SMA 50 Ω End launch SMA Standard Banana Jack, 6092 6092 Keystone Insulated, Black SLVUAN8 – April 2016 TPD1E04U04 Evaluation Module Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated... - Page 8 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
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