Nexcom NDiS 541 User Manual page 81

Appendix C: Watchdog Timer
Bit Read / Write
2 R/W Enable the rising edge of KBC reset (P20) to is-
sue time-out event.
0: Disable
1: Enable
1 R/W Disable/Enable the WDTO# output low pulse to
the KBRST# pin (PIN60)
0: Disable
1: Enable
0 Reserved
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Description
CR F6h. (WDTO# Counter Register; Default 00h)
Bit Read / Write
7-0 R/W Watchdog Timer Time-out value.
Writing a non-zero value to this register causes
the counter to load the value to Watchdog
Counter and start counting down.
If bits 7 and 6 of CR F7h are set, any Mouse
Interrupt or Keyboard Interrupt event will also
cause the reload of previously-loaded non-zero
value to Watchdog Counter and start count-
ing down. Reading this register returns current
value in Watchdog Counter instead of Watchdog
Timer Time-out value.
00h: Time-out Disable
01h: Time-out occurs after 1 second/minute
02h: Time-out occurs after 2 seconds/minutes
03h: Time-out occurs after 3 seconds/minutes
.......................................................................
FFh: Time-out occurs after 255 seconds/minutes
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Description
NDiS 541 User Manual