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TENX TECHNOLOGY 82314BW User Manual

8 bit microcontroller
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TM59PA80
8 bit
Microcontroller
TM59PA80
User's Manual
tenx technology, inc.
tenx technology, inc.
0
Rev 1.2, 2007/03/06

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Summary of Contents for TENX TECHNOLOGY 82314BW

  • Page 1 TM59PA80 8 bit Microcontroller TM59PA80 User’s Manual tenx technology, inc. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 2: Table Of Contents

    4. 8-Bit PWM................... 65 5. Analog to Digital Converter............67 6. I/O Ports....................69 7. LCD Controller .................. 75 8. Buzzer Out ..................80 9. Serial I/O..................... 82 10. Electrical Characteristics............86 11. Packaging Information ..............92 tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 3: Overview

    • 10. Buzzer Out Frequency Selectable Buzzer Output • 11. LCD Controller/Driver 8 COM X 16 SEG • 4 COM X 20 SEG • 3 COM X 20 SEG • tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 4 2.0 V to 5.5 V at 0.4 ~ 4.2 MHz • 2.5 V to 5.5 V at 0.4 ~ 12 MHz • 17. Package Type 44-pin QFP • 44-pin LQFP • 42-pin SDIP • 40-pin DIP • tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 5 Port D 8-bit Timer1 Port E 8-bit Timer2 8K(14Bit) 20 Byte Port F 192 Byte Program SRAM Memory Buffer 10 bit ADC 6 ch Port G 8-bit Buzzer Controller < Figure 1-1. Block Diagram > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 6 UM-TM59PA80_E < Figure 1-2. Pin Assignment Diagram (44-Pin QFP Package) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 7 UM-TM59PA80_E < Figure 1-3. Pin Assignment Diagram (44-Pin LQFP Package) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 8 AD2/INT6/PB.2 PF.3/SEG15 AD3/INT7/PB.3 PF.2/SEG14 PF.1/SEG13 42 SDIP PF.0/SEG12 PE.7/SEG11 PE.6/SEG10 nTEST PE.5/SEG9 PE.4/SEG8 PE.3/SEG7 nRESET PE.2/SEG6 PWM0/PC.3 PE.1/SEG5 SI/PC.2 PE.0/SEG4 SO/SEG0/PC.1 PD.0/SEG3/INT9 SCLK/SEG1/PC.0 PD.1/SEG2/INT8 < Figure 1-4. Pin Assignment Diagram (42-Pin SDIP Package) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 9 UM-TM59PA80_E < Figure 1-5. Pin Assignment Diagram (40-Pin DIP Package) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 10 External interrupt input port PD.0-1 PWM0 8-Bit high speed PWM output PC.3 T0OUT Timer0 match output PA.0 ADC0-ADC5 A/D converter input PB.0-3, PA.4-5 <Table 1-1. PIN Description> < I: Input; O: Output; I/O: Bi-direction; P: Power > tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 11: Clock Scheme And Instruction Cycle

    (f ) to a sub clock (f ) and to stop the main clock. To do this, the following steps must be taken to switch from a sub clock to the main clock. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 12: Addressing Mode

    For the other instructions updating PC[7:0], the PC[12:8] keeps unchanged. The STACK is 13-bit wide and 6-level in depth. The CALL instruction and Hardware interrupt will push STACK level in order, while the RET/RETI/RETLW instruction pops the STACK level in order. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 13: Alu And Working (W) Register

    Depending on the instruction executed, the ALU may affect the values of Carry(C), Digit Carry (DC), and Zero (Z) Flags in the STAT register. The C and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 14: Status Register

    “RETI” instruction. That is, at least one instruction in main program is executed before service the pending interrupt. The interrupt event is edge trigged. F/W must clear the interrupt event register while serves the interrupt routine. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 15: Reset

    CLRWDT executed in a period of 2 oscillator’s cycle (256 msec for 8.192MHz crystal). The Watchdog Timer does not work in Power-down mode to provide wake-up function. It is only designed to prevent F/W goes into endless loop. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 16: Power-Down Mode

    Working Register Aero Flag Carry Flag Decimal Carry Flag Program Counter Top Of Stack Global Interrupt Enable Flag (i-Flag) Option Field Contents Bit Field ← Assign direction < List 1-1 OP-CODE Field Description > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 17 Return with Literal "k" in W 01 1000 kkkk kkkk Enter STOP mode, Clock oscillation SLEEP 00 0000 1000 1010 stops XORLW XOR Literal "k" with W 01 1111 kkkk kkkk < List 1-2 Instruction Summary > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 18 The contents of W register are AND’ed with the eight-bit literal 'k'. The result is placed in the W register. Cycle Example ANDLW 0x5F B : W = 0xA3 A : W = 0x03 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 19 Operation (f.b) ← 1 Status Affected OP-Code 01 001b bbff ffff Description Bit ’b’ in register ’f’ is set. Cycle Example BSF FLAG_REG, 7 B : FLAG_REG = 0x0A A : FLAG_REG = 0x8A tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 20 The eleven-bit immediate address is loaded into PC bits <11:0>. CALL is a two-cycle instruction. Cycle Example LABEL1 CALL SUB1 B : PC = LABEL1 A : PC = SUB1, TOS = LABEL1+1 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 21 WDTE ← 00h Status Affected OP-Code 00 0000 0000 0100 Description CLRWDT instruction enables and resets the Watchdog Timer. Cycle Example CLRWDT B : WDT counter = ? A : WDT counter = 0x00 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 22 Cycle 1 or 2 Example LABEL1 DECFSZ CNT, 1 B : PC = LABEL1 GOTO LOOP A : CNT = CNT − 1 CONTINUE if CNT=0, PC = CONTINUE if CNT≠0, PC = LABEL1+1 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 23 Cycle 1 or 2 Example LABEL1 INCFSZ CNT, 1 B : PC = LABEL1 GOTO LOOP A : CNT = CNT + 1 CONTINUE if CNT=0, PC = CONTINUE if CNT≠0, PC = LABEL1+1 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 24 (W) ← (f) Status Affected OP-Code 00 1000 0fff ffff Description The contents of register f are moved to W register. Cycle Example MOVF FSR, 0 B : W = ? A : W ← f tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 25 B : REG1 = 0xFF, W = 0x4F A : REG1 = 0x4F, W = 0x4F No Operation Syntax Operands Operation No Operation Status Affected OP-Code 00 0000 0000 0000 Description No Operation Cycle Example tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 26 Description Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Cycle Example RETURN A : PC = TOS tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 27 SLEEP Go into standby mode, Clock oscillation stops Syntax SLEEP Operands Operation Status Affected OP-Code 00 0000 0000 0011 Description The processor is put into SLEEP mode with the oscillator stopped. Cycle Example SLEEP tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 28 If the contents of register ‘f’ is 0, Zero flag is set to 1. Cycle Example TESTZ REG1 B : REG1 = 0, Z = ? A : REG1 = 0, Z = 1 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 29 W register. If ‘d’ is 1, the result is stored back in register ‘f’. Cycle Example XORWF REG 1 B : REG = 0xAF, W = 0xB5 A : REG = 0x1A, W = 0xB5 tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 30: Control Registers

    T0CON PDCON LCDCON T0DATA PINTD0 LPCON T1CON PINTD1 LVDCON T1DATA PINTD2 ADCDATL T2CON INTCON0 ADCDATH BZCON INTCON1 SIOPS ADCCON SIOCON STOPCON − SIODAT INTPND0 INTPND1 SYSTEM Use Only GPR0 GPR1 GPR2 GPR3 GPR4 GPR5 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 31 — ADC Data Register Low Byte See Also Reset Value − − − − − − − − − − − − − − Description PWM1 Period Data Low Byte ADC Data Value Lower 2Bit tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 32 Bank1, 01H — Clock Control Register See Also Reset Value − − − − − − − − − − − − R/W R/W Description Not Used Divided by Selection Bits for CPU Clock frequency tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 33 R/W R/W R/W R/W R/W R/W R/W R/W Description General Purpose Register GPR0−5 are mirrored all bank. It is useful to pass arguments to SUB routine or backup Working register (W) and STAT register in ISR or SUB routine. tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 34 EXTINT5 Interrupt Enable Bit Disable Enable EXTINT4 Interrupt Enable Bit Disable Enable EXTINT3 Interrupt Enable Bit Disable Enable EXTINT2 Interrupt Enable Bit Disable Enable EXTINT1 Interrupt Enable Bit Disable Enable EXTINT0 Interrupt Enable Bit Disable Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 35 Timer 1 Match Interrupt Enable Bit Disable Enable Timer 0 Match Interrupt Enable Bit Disable Enable Not Used SIO Interrupt Enable Bit Disable Enable EXTINT9 Interrupt Enable Bit Disable Enable EXTINT8 Interrupt Enable Bit Disable Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 36 No interrupt pending (read) / Pending bit clear (write) Interrupt is pending (read) / No effect (write) EXTINT0 Interrupt Pending Bit No interrupt pending (read) / Pending bit clear (write) Interrupt is pending (read) / No effect (write) tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 37 No interrupt pending (read) / Pending bit clear (write) Interrupt is pending (read) / No effect (write) EXTINT8 Interrupt Pending Bit No interrupt pending (read) / Pending bit clear (write) Interrupt is pending (read) / No effect (write) tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 38 1/8 duty, 1/5 bias ( COM0−COM7, SEG0−SEG15 ) LCD Clock Selection Bits ( 256 Hz, f = 32.768 Hz) ( 512 Hz, f = 32.768 Hz) (1024 Hz, f = 32.768 Hz) (2048 Hz, f = 32.768 Hz) tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 39 SEG3 / PORTD.0 Selection Bit Normal I/O SEG Enable SEG2 / PORTD.1 Selection Bit Normal I/O SEG Enable SEG1 / PORTC.0 Selection Bit Normal I/O SEG Enable SEG0 / PORTC.1 Selection Bit Normal I/O SEG Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 40 RESET Enable Bit Disable Reset Enable Reset Voltage Level Status Bit is lower than reference voltage is higher than reference voltage Reference Voltage Selection Bit 11011 2.3V 10000 3.0V 01110 3.9V Others Not Used tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 41 Main oscillator RUN Main oscillator STOP Sub Oscillator Control Bit Sub oscillator RUN Sub oscillator STOP System Clock Selection Bit Main oscillator select Sub oscillator select Idle Mode Control Bit No Effect Enter Idle Mode tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 42 Push-pull output Open-drain output Clock Output Port A.1 Configuration Bits Schmitt-trigger Input / INT1 / T0CLK Input Push-pull output Open-drain output Port A.0 Configuration Bits Schmitt-trigger Input / INT0 Push-pull output Open-drain output T0OUT tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 43 Schmitt-trigger Input Push-pull output Open-drain output ADC4 Bank0, 05H — Port A Data Register Related Register Reset Value − − − − R/W R/W R/W R/W R/W R/W Description Not Used Port A.5-0 Data Bits tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 44 Port A.3 Pull-up Enable Bit Pull-up Disable Pull-up Enable Port A.2 Pull-up Enable Bit Pull-up Disable Pull-up Enable Port A.1 Pull-up Enable Bit Pull-up Disable Pull-up Enable Port A.0 Pull-up Enable Bit Pull-up Disable Pull-up Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 45 Schmitt-trigger Input / INT6 Push-pull output Open-drain Output ADC2 Port B.1 Configuration Bits Schmitt-trigger Input / INT5 Push-pull output Open-drain Output ADC1 Port B.0 Configuration Bits Schmitt-trigger Input / INT4 Push-pull output Open-drain Output ADC0 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 46 Port B.3 Pull-up Enable Bit Pull-up Disable Pull-up Enable Port B.2 Pull-up Enable Bit Pull-up Disable Pull-up Enable Port B.1 Pull-up Enable Bit Pull-up Disable Pull-up Enable Port B.0 Pull-up Enable Bit Pull-up Disable Pull-up Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 47 Open-drain Output SCLK Out Bank0, 07H — Port C Data Register Related Register Reset Value − − − − − − − − R/W R/W R/W R/W Description Not Used Port C.3-0 Data Bits tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 48 Not Used Port D.1 Configuration Bits Schmitt-trigger Input / INT9 Push-pull output Open-drain Output Input mode with Pull-Up Port D.0 Configuration Bits Schmitt-trigger Input / INT8 Push-pull output Open-drain Output Input mode with Pull-Up tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 49 Open-drain Output Input mode with Pull-Up Port E.1 Configuration Bits Schmitt-trigger Input Push-pull output Open-drain Output Input mode with Pull-Up Port E.0 Configuration Bits Schmitt-trigger Input Push-pull output Open-drain Output Input mode with Pull-Up tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 50 Schmitt-trigger Input Push-pull output Open-drain Output Input mode with Pull-Up Bank0, 0BH — Port E Data Register Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Port E.7-0 Data Bits tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 51 Open-drain Output Input mode with Pull-Up Port F.1 Configuration Bits Schmitt-trigger Input Push-pull output Open-drain Output Input mode with Pull-Up Port F.0 Configuration Bits Schmitt-trigger Input Push-pull output Open-drain Output Input mode with Pull-Up tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 52 Schmitt-trigger Input Push-pull output Open-drain Output Input mode with Pull-Up Bank0, 0CH — Port F Data Register Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Port F.7-0 Data Bits tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 53 Open-drain Output Input mode with Pull-Up Bank0, 0DH — Port G Data Register Related Register Reset Value − − − − − − − − R/W R/W R/W R/W Description Port G.3-0 Data Bits tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 54 Port A.1 EXTINT1 Interrupt Signal Selection Bit Falling Edge Interrupt Enable Rising Edge Interrupt Enable Rising/Falling Edge Interrupt Enable Port A.0 EXTINT0 Interrupt Signal Selection Bit Falling Edge Interrupt Enable Rising Edge Interrupt Enable Rising/Falling Edge Interrupt Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 55 Port D.1 EXTINT9 Interrupt Signal Selection Bit Falling Edge Interrupt Enable Rising Edge Interrupt Enable Rising/Falling Edge Interrupt Enable Port D.0 EXTINT8 Interrupt Signal Selection Bit Falling Edge Interrupt Enable Rising Edge Interrupt Enable Rising/Falling Edge Interrupt Enable tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 56 Bank2, 0DH — PWM0 Data Register Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description PWM Period Data XXXXXX Period Data Extension Cycle Selection Bit − 1, 3 1, 2, 3 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 57 Tx at rising edge, Rx at falling edge SIO Counter Clear and Shift Start Bit No effect Clear 3-bit counter and start shifting SIO Shift Operation Enable Bit Disable shifter and clock counter Enable shifter and clock counter Not Used tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 58 Bank 0 Bank 1 Bank 2 Not Used Not Used (Must keep always ‘0’) Zero Flag(Z) Zero Flag Decimal Carry Flag(DC) Decimal Carry Flag or Decimal/Borrow Flag Carry Flag(C) Carry Flag or Borrow Flag tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 59 T0CLK Timer 0 Counter Clear Bit (Auto Cleared) No effect Clear the timer 0 counter (when write) T0Data load to T0Buf Timer 0 Start/Stop Control Bit Stop Timer 0 Start/Resume Timer 0 Not Used tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 60 Timer 1 Start/Stop Control Bit Stop Timer 0 Start/Resume Timer 0 Not Used T0DATA Bank0, 0FH — TIMER 0 Data Register See Also Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Period Data tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 61 WatchDog Timer Control Register This register is not physical register. The WatchDog timer can be enabled and refreshed by CLRWDT or writing any value into this register. The CLRWDT instruction is equivalent to “MOVWF WDTE”. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 62: Bit Timer

    T0OUT T0 Match T1 Match T0 Comparator T1 Comparator T1PND T0CON.7 T0 BUF T1 BUF T0PND INTCON1.5 T0INT T0DATA T1DATA T1INT INTCON1.4 T1 Match T0CON.7 < Figure 3-1. Timer 0, 1 Block Diagram > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 63 T0OUT, and counting resumes. T0DATA Match T0CNT T0DATA Counter Change Clear T0DATA Buffer Reload T0OUT < Figure 3-2. 8-Bit Interval Mode Timing diagram (Timer 0 ) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 64 ;Timer 0 Match Interrupt Enable Bit CALL BANK_0 T0CON,3 ;Timer 0 Counter Clear STAT,7 ;Enable All Interrupts T0CON,2 ;Start Timer 0 LOOP: GOTO LOOP ;*************************************************************************************************************************** BANK_0: STAT,4 STAT,5 ;RAM_BANK_0 BANK_1: STAT,4 STAT,5 ;RAM_BANK_1 BANK_2: STAT,4 STAT,5 ;RAM_BANK_2 ;*************************************************************************************************************************** tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 65 — Timing Tests in High-Speed Mode — Overflow interrupt generation ( 1s, 0.5s, 0.25s, 3.91ms) — Timer 2 control register, T2CON T2CON.7 INTCON1.6 /128 INTPND1.6 T2CON.0 Interval T2CON.3-2 Selector Frequency Divider < Figure 3-3. Timer 2 Block Diagram > tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 66: Bit Pwm

    "extend" the duty cycle of the PWM output. The " extension " value is one extra clock period at specific cycles (see Table 4-1). PWM0DAT.1-0 Extended Cycle None 1, 3 1, 2, 3 < Table 4-1. PWM output extended cycle > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 67 ; Data = 1, Extension = 1 PCCON, 6 PCCON, 7 ; Select PCCON.76 '11' PWM0 Out. CLRF PWM0CON /64, 8-bit Overflow Reload, PWM Stop PWM0CON, 1 ; PWM0 Counter Clear PWM0CON, 0 ; PWM0 Start tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 68: Analog To Digital Converter

    EOC Flag Selection (ADCCON.0) (ADCCON.2-1) (ADCCON.3) (ADCCON.7-4) ADC0 Successive ADC1 Approximation Circuit ADC2 Analog Comparator ADC3 ADC4 ADC5 Conversion Result D/A Converter ADCDATH ADCDATL < Figure 5-1. Analog to Digital Converter Block Diagram > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 69 ; Configure PB.0 ADC Input 0 ADCCON, 0 ; Start Conversion ADC_LOOP: BTFSS ADCCON, 3 GOTO ADC_LOOP ; Wait until EOC bit is set ; Converted value can be read from ADDATL and ; ADDATH. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 70: I/O Ports

    SEG1, SCLK Schmitt trigger input, Push-pull output, Open-Drain output, PORTC SEG0, SO Schmitt trigger input, Push-pull output, Open-Drain output, SI Schmitt trigger input, Push-pull output, Open-Drain output, PWM0 < Table 6-1. Port Configuration Overview ①> tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 71 Schmitt trigger Input, Push-pull output, Open-Drain output, COM0 Schmitt trigger Input, Push-pull output, Open-Drain output, COM1 PORTG Schmitt trigger Input, Push-pull output, Open-Drain output, COM2 Schmitt trigger Input, Push-pull output, Open-Drain output, COM3 < Table 6-1. Port Configuration Overview ②> tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 72 Resister Noise Filter nRESET < Figure 6-1. Pin Circuit Type R > Pull-up Open-drain Enable Enable P-CH Data N-CH Output Disable Digital Input External Interrupt Input < Figure 6-2. Pin Circuit Type B > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 73 Open-drain Enable Enable P-CH Data N-CH Output Disable Digital Input Interrupt Input Enable ADC Input < Figure 6-3. Pin Circuit Type C > COM/SEG Output Disable < Figure 6-4. Pin Circuit Type D > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 74 Interrupt Input < Figure 6-5. Pin Circuit Type D-1 > Pull-Up Resister Open-Drain Enable Pull-Up Enable Data LCD Output Enable COM/SEG Circuit D Output Disable Digital Input < Figure 6-6. Pin Circuit Type D-2 > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 75 LPCON register. PORTG Port G has 4-bit I/O Pins. It can be used for normal I/O (Schmitt trigger Input, push-pull output, open-drain output) or LCD COM output. LCD Function can be selected in LPCON register. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 76: Lcd Controller

    LCD display is enabled even during main clock stop and idle modes. Duty Dot Count COM0 ~ COM2 SEG0 ~ SEG19 COM0 ~ COM3 SEG0 ~ SEG19 COM0 ~ COM7 SEG0 ~ SEG15 < Table 7-1. COM & SEG per Duty > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 77 And the data can be transferred to the segment signal pins automatically without program control. COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG0 SEG1 SEG2 SEG17 SEG18 SEG19 < Figure 7-2. LCD Buffer Organization > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 78 SEG3 [23h] SEG4 [24h] LCD1 COM0 LCD2 LCD4 LCD1 COM1 LCD2 LCD4 LCD1 COM2 LCD2 LCD4 LCD1 SEG0 LCD2 LCD4 +1/4V SEG0-COM0 - 1/4V < Figure 7-3. LCD Signal (1/8 Duty, 1/4 Bias) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 79 LCD1 LCD2 COM2 LCD3 LCD4 LCD1 LCD2 COM3 LCD3 LCD4 LCD1 LCD2 SEG0 LCD3 LCD4 LCD1 LCD2 SEG1 LCD3 LCD4 +1/3V COM0-SEG0 - 1/3V < Figure 7-4. LCD Signal (1/4 Duty, 1/3 Bias) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 80 LCD1 LCD2 COM2 LCD3 LCD4 LCD1 LCD2 SEG0 LCD3 LCD4 LCD1 LCD2 SEG1 LCD3 LCD4 LCD1 LCD2 SEG2 LCD3 LCD4 +1/3V COM0-SEG0 - 1/3V < Figure 7-5. LCD Signal (1/3 Duty, 1/3 Bias) > tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 81: Buzzer Out

    /2/Prescaler Ratio/(Period Data + 1) Example 8-1> Output frequency calculation System Clock (f ) : 8.192MHz Prescaler Ratio (BZCON.7-6) : 11 (f /64), Period Data (BZCON.5-0) : 9 8.192M / 2 / 64 / (9+1) = 64000 (Hz) tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 82 ; Set PA.3 Input mode. Buzzer Disable PACONL, 6 Buzzer Counter Buzzer Buzzer Data Buzzer Data Buzzer Change Change Disable Enable Before > After Before < After Buffer Reload Buzzer Output < Figure 8-2. Timing Diagram > tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 83: Serial I/O

    The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. < Figure 9-1. SIO Block Diagram > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 84 The prescaler register for serial I/O interface module, SIOPS. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (f /4)/(Prescaler value + 1), or SCLK input clock. tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 85 UM-TM59PA80_E SCLK Transmit Complete SET SIOCON.3 < Figure 9-2. SIO Transmit/Receive Mode (Tx at falling edge) > SCLK Transmit Complete SET SIOCON.3 < Figure 9-3. SIO Transmit/Receive Mode (Tx at rising edge) > tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 86 UM-TM59PA80_E SCLK High Impedance Transmit Complete SET SIOCON.3 < Figure 9-4. SIO Receive-Only Mode (Rising edge start) > tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 87: Electrical Characteristics

    − − Current(pin low) , XT = 0 V −20 ILL2 μA Output Leakage All output pins − − Current(pin high) Output Leakage All output pins = 0 V − − −3 Current(pin low) tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 88 = 3 V ± 10 % Idle Sub Clock (32768 Hz) μA = 3 V ± 10 % = 5 V ± 10 %, STOP mode = 3 V ± 10 %, STOP mode tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 89 External RC = 3.0 V − SUB Clock − 32.768 NOTE: 1. Tolerance: ±10 % at T = 25°C External Oscillator Circuit External R-C Oscillator (Crystal or Ceramic) Sub-Clock Oscillator Circuit (Crystal or Ceramic) tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 90 External SCLK Source SI setup time SCLK high Internal SCLK Source External SCLK Source SI hold time SCLK high Internal SCLK Source Output delay External SCLK Source − − SCLK to SO Internal SCLK Source SCLK tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 91 −40 ° 10-7. LVD Circuit Characteristics (T C, V = 2.0V to 5.5V) Parameter Symbol Unit LVD reference Voltage − − LVD Hysteresis Voltage − − ±0.3 HYST Low Voltage μs − − Detection time tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 92 (Note-2) Current = 5 V stop mode − NOTE: 1. “Conversion time” is the time required from the moment a conversion operation starts until it ends. 2. I is operating current during A/D conversion. tenx technology, inc. Rev 1.2, 2007/03/06...

  • Page 93: Packaging Information

    Pin Number: 42 Code: 42 (2). Pin Number: 40 Code: 40 (3). “C”: Reserve (Must write be “C”) “Z”: Package material Package material: Pb-free Code: W (1). Package material: Green Package Code: G (2). tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 94 11-1. 44-QFP Package Dimension 44 lead, Quad Flat Package Dimension in Millimeters 0 - 8° 13.20 ± 0.30 10.00 ± 0.20 44-QFP 0.35 ± 0.10 0.80 1.00 MIN 0.05 2.05 ± 0.10 MAX 2.30 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 95 UM-TM59PA80_E 11-2. 42-SDIP Package Dimension 42 lead, Shrink Dual In-line Package Dimension in Millimeters 15.24 42 - SDIP 0 - 15° MAX 39.50 39.10 ± 0.20 1.77 0.50 ± 0.10 1.778 1.00 ± 0.10 tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 96 UM-TM59PA80_E 11-3. 44-LQFP Package Dimension 44 lead, Shrink Dual In-line Package Dimension in Millimeters tenx technology, inc. Rev 1.2, 2007/03/06...
  • Page 97 UM-TM59PA80_E 11-4. 40-DIP Package Dimension 40 lead, Shrink Dual In-line Package Dimension in Millimeters tenx technology, inc. Rev 1.2, 2007/03/06...

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