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TENX TECHNOLOGY TM57PE10 User Manual

8-bit microcontroller
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UM-TM57PE10_E
Advance Information
8-Bit Microcontroller
TM57PE10
8-Bit Microcontroller
User Manual
tenx reserves the right to change or discontinue the manual and online documentation to this product herein to improve reliability,
function or design without further notice. tenx does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. tenx products are not designed,
intended, or authorized for use in life support appliances, devices, or systems. If Buyer purchases or uses tenx products for any such
unintended or unauthorized application, Buyer shall indemnify and hold tenx and its officers, employees, subsidiaries, affiliates and
distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that tenx was
negligent regarding the design or manufacture of the part.
tenx technology inc.
1
Preliminary
Rev 1.4, 2012/01/19

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Summary of Contents for TENX TECHNOLOGY TM57PE10

  • Page 1 Preliminary Rev 1.4, 2012/01/19...

  • Page 2: Amendment History

    3. Add 16-pin Package Dimension. 1. Add the Electrical Characteristics specs in the Features section. V1.4 Jan, 2012 2. Add description in Reset section. 4. Merge the information about LVR Circuit Characteristics into DC Characteristics table. tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 3: Table Of Contents

    4. I/O Port ........................27 4.1 PA0-2 ........................27 4.2 PA3-6, PB0-7 ...................... 28 4.3 PA7 ........................28 MEMORY MAP ........................29 F-Plane ........................... 29 R-Plane ........................... 31 INSTRUCTION SET ......................33 ELECTRICAL CHARACTERISTICS ................. 45 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 4 PACKAGING INFORMATION ................... 51 14-DIP Package Dimension .................... 52 14-SOP Package Dimension ..................52 16-DIP Package Dimension .................... 53 16-SOP Package Dimension ..................54 18-DIP Package Dimension .................... 55 18-SOP Package Dimension ..................55 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 5: Features

     Stop Mode: All Clocks stop, Wake-up Timer is disabled or enabled Dual System Clock  FIRC + SIRC  FIRC + SXT  FIRC + XRC  FXT + SIRC  XRC + SIRC tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 6  Watchdog timer can be disabled/enabled in STOP mode I/O Ports  CMOS Output  Pseudo-Open-Drain or Open-Drain Output  Schmitt Trigger Input with/without pull-up resistor Instruction set: 36 Instructions Package Types: 14-DIP/SOP, 16-DIP/SOP, 18-DIP/SOP tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 7: Block Diagram

    5-LEVEL Register Register Instruction STACK File File Register Instruction F-plane Indirect Decoder Address FXT/SXT STATUS FIRC CLOCK GEN. Timeout & TIMING RESET CTRL T0I/PA2 TIMER0 PRESCALER Analog 8-bit 8-bit TIMER2 TIMER0 PWM0 PWM1 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 8: Pin Assignment

    TM57PE10 INT1/PB0 PB5/PWM1 IN0-/PB1 PB4/CMPO IN1-/PB2 PB3/IN+ PWM0/PA1 PA0/INT0 T0I/PA2 PA4/Xin/Xrc VPP/nReset/INT2/PA7 PA3/Xout/CLKO INT1/PB0 TM57PE10 IN0-/PB1 IN1-/PB2 PB5/PWM1 IN+/PB3 PB4/CMPO PWM0/PA1 PA0/INT0 T0I/PA2 PA4/Xin/Xrc VPP/nReset/INT2/PA7 PA3/Xout/CLKO TM57PE10 INT1/PB0 IN0-/PB1 IN1-/PB2 PB5/PWM1 IN+/PB3 PB4/CMPO tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 9: Pin Description

    VDD, VSS Power Voltage input pin and ground PROM programming high voltage input INT0–INT2 External interrupt input PWM0–PWM1 PWM output IN0-, IN1-, IN+ Comparator voltage input CMPO Comparator output Clock input to Timer0 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 10: Functional Description

    FSR register (FSR is a pointer). The first half of F-Plane is bit-addressable, while the second half of F-Plane is not bit-addressable. R-Plane F-Plane Bit Addressable MOVWR Instruction Write Only SRAM Bit Addressable SRAM tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 11: Programming Counter (Pc) And Stack

    ALU may affect the values of Carry (C), Digit Carry (DC), and Zero (Z) Flags in the STATUS register. The C and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction. Note: /Borrow represents inverted of Borrow register. /Digit Borrow represents inverted of Digit Borrow register. tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 12: Status Register

    0: no carry result occurs C: Carry Flag or /Borrow Flag ADD instruction SUB instruction 1: a carry occurs from the MSB 1: no borrow 0: no carry 0: a borrow occurs from the MSB tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 13: Interrupt

    An interrupt event will set its individual pending flag; no matter its interrupt enable control bit is 0 or 1. Because TM57PE10 has only 1 vector, there is not an interrupt priority register. The interrupt priority is determined by F/W.

  • Page 14: Chip Operation Mode

    UM-TM57PE10_E Advance Information 8-Bit Microcontroller 2. Chip Operation Mode 2.1 Reset The TM57PE10 can be RESET in four ways. － Power-On-Reset － Low Voltage Reset (LVR) － External Pin Reset (PA7) － Watchdog Reset (WDT) After Power-On-Reset, all system and peripheral control registers are then set to their default hardware Reset values.

  • Page 15: System Configuration Register (Syscfg)

    Enable External pin Reset Disable External pin Reset to use as input pin WDTE: WDT Reset Enable Enable WDT Reset Disable WDT Reset FIRC: 1:FIRCCLK=8 MHz, 0: FIRCCLK=4 MHz FIRCF: Fast Internal RC Frequency adjustment control tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 16: Prom Re-Use Rom

    WDT/WKT Timer is working or not depends on F/W setting. The Power down mode can be terminated by Reset, or enabled Interrupts (External pins and WKT interrupt) or PA1-6 and PB1-6 pins low level wake up. tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 17: Dual System Clock

    SYSCFG[9:8] Fast Mode: After power on or reset, TM57PE10 enters fast mode. In fast mode, TM57PE10 can select FXT, XRC or FIRC as its CPU clock by SYSCFG bit9 and bit8 setting. Besides, firmware can also enable or disable the slow clock for the Timer2 system operating. In this mode, the program is executed using fast clock as CPU clock.

  • Page 18: Dual System Clock Modes Transition

    UM-TM57PE10_E Advance Information 8-Bit Microcontroller 2.6 Dual System Clock Modes Transition TM57PE10 is operated in one of four modes: Fast Mode, Slow Mode, Idle Mode, and Stop Mode. Modes Transition Diagram: SUBE= 0 or 1 SUBE=0 SELSUB=0 SELSUB=0 or 1...
  • Page 19 PAD4 PAE4 nPAPU4 ※ ※ ※ ※ ※ ※ FIRC SIRC FIRC ※ ※ ※ FIRC ※ ※ ※ ※ ※ ※ SIRC ※ ※ ※ ※ ※ ※ SIRC ※：Don’t care tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 20: Peripheral Functional Block

    If the user program needs the MCU totally shuts down for power conservation in sleep mode, the following setting of control bits should be followed. Mode WDTE WKTIE Watchdog RC Oscillator Stop Normal Mode Stop Sleep Mode Stop tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 21: Timer0: 8-Bit Timer/Counter With Pre-Scale (Psc)

    When Fosc = 4 MHz, div = TM0PSC [3:0] when select 4’b0000 = 1 (4M/2)/1/256 = 2M/256 Hz = 7.8125 KHz Timer0 interrupt frequency by T0I: (T0I) / div / 256 Note: T0I frequency <= Fosc / 4 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 22: Timer2: 15-Bit Timer

    PWM0DUTY to PWM0BUF, CLRPWM0 bit must be cleared so that the PWM0 counter can count. Figure shows the block diagram of PWM0. PWM0DUTY PA1O A<=B PWM0BUF PWM0O CLRPWM0 CLRPWM0 PWM0E CLRPWM0 PWM0PERIOD PWM0OVF PWM0I Fosc/1 Fosc/2 PWM0CNT Fosc/4 Fosc/8 PWM0IE PWM0PSC[1:0] CLRPWM0 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 23 Note: The div variable represents the prescale factor by PWM0PSC [1:0] select value (1, 2, 4, 8) div = PWM0PSC [1:0] when select 2’b00 = 1 When PWM0PERIOD = FFH, Fosc = 4 MHz, PWM0 output frequency = (4M)/1/256 = 15.625 KHz tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 24: Pwm1: 8-Bit Pwm

    PWM1 output duty = [PWM1DUTY / 256] When PWM1DUTY = 80H, PWM1 output duty will be 1/2 PWM1 output frequency = (Fosc) / 256 When Fosc = 4 MHz, PWM1 output frequency = (4M)/256 = 15.625 KHz tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 25: Analog Comparator

    8-Bit Microcontroller 3.6 Analog Comparator TM57PE10 includes an analog comparator. It can be enabled by CMPEN which is in R-Plane 17H Bit7. The analog comparator compares the input values on the positive pin Vin+ and negative pin Vin-. When the voltage on positive pin is higher than the voltage on the negative pin, the analog comparator out (CMPO) is set.

  • Page 26: System Clock Oscillator

    1 uF and 0.1 uF very close to VDD/VSS pins improves the stability of clock and the overall system. External Oscillator Circuit External RC Oscillator (Crystal or Ceramic) 0.1uF Internal RC Mode tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 27: I/O Port

    Modify-Write” instruction includes BSF, BCF and all instructions using F-Plane as destination. nPAPU DATA Write WR_nPAPU pull-up WR_PAE SYS_RESETn Port Delay Pre-Driver 1 CLK WR_PAD DATA Read RD_PAD Read_Modify_Write PA0-2, nPAPU=0 Drive Drive Drive Drive Drive Drive 1 CLK tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 28: Pa3-6, Pb0-7

    Drive Drive Drive Drive 4.3 PA7 PA7 can be only used in Schmitt-trigger input mode. The pull-up resistor is always connected to this pin. SYS_RESETn DATA pull-up Write WR_PAD DATA Read RD_PAD Read_Modify_Write tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 29: Memory Map

    0: clear this flag; write 1: no action INT2 interrupt event pending flag, set by H/W at INT2 pin’s falling edge XINT2 09.2 write 0: clear this flag; write 1: no action tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 30 14.4 Reserved CMPST 14.3 Comparator output status CLRTM2 14.2 Write 1 to clear Timer2, auto cleared by H/W STOPTM0 14.1 Stop Timer0 counting CLRPWM0 14.0 PWM0 clear and hold SRAM 20~4F Internal RAM tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 31: R-Plane

    00: SIRC Frequency is 151 KHz, @5V; 115 KHz, @3V 01: SIRC Frequency is 37 KHz, @5V; 29 KHz, @3V 10: SIRC Frequency is 9.4 KHz, @5V; 7.2 KHz, @3V 11: SIRC Frequency is 2.4 KHz, @5V; 1.9 KHz, @3V tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 32 Comparator Vin- input select, 0: IN0-, 1: IN1- Comparator Vin+ input select 0000: VSS 0001: VDD * 1/16 CMPINPS 17.3~0 1110: VDD * 14/16 1111: IN+ PBWKUP 18.6~1 Enable PB6~PB1 pin low level wake up tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 33: Instruction Set

    Destination selection field, 0: Working register, 1: Register file Working Register Zero Flag Carry Flag Decimal Carry Flag Program Counter Top Of Stack Global Interrupt Enable Flag (i-Flag) Option Field Contents Bit Field Before After ← Assign direction tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 34 RETLW Return with Literal in W 01 1000 kkkk kkkk Go into standby mode, Clock SLEEP TO,PD 00 0000 0000 0011 oscillation stops XORLW 01 1111 kkkk kkkk XOR Literal "k" with W tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 35 If 'd' is 1, the result is stored back in register 'f'. Cycle Example ANDWF FSR, 1 B : W = 0x17, FSR = 0xC2 A : W = 0x17, FSR = 0x02 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 36 1 or 2 Example LABEL1 BTFSS FLAG, 1 B : PC = LABEL1 TRUE GOTO SUB1 A : if FLAG.1 = 0, PC = TRUE FALSE if FLAG.1 = 1, PC = FALSE tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 37 WDT/WKT Timer ← 00h Operation Status Affected TO, PD OP-Code 00 0000 0000 0100 Description CLRWDT instruction clears the Watchdog/Wakeup Timer Cycle Example CLRWDT B : WDT counter = ? A : WDT counter = 0x00 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 38 GOTO is an unconditional branch. The 12-bit immediate value is loaded into PC bits <11:0>. GOTO is a two-cycle instruction. Cycle Example LABEL1 GOTO SUB1 B : PC = LABEL1 A : PC = SUB1 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 39 W register. If 'd' is 1, the result is placed back in register 'f'. Cycle Example IORWF RESULT, 0 B : RESULT = 0x13, W = 0x91 A : RESULT = 0x13, W = 0x93, Z = 0 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 40 00 0000 00rr rrrr Description Move data from W register to register 'r'. Cycle Example MOVWR REG1 B : REG1 = 0xFF, W = 0x4F A : REG1 = 0x4F, W = 0x4F tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 41 (the return address). This is a two-cycle instruction. Cycle Example CALL TABLE B : W = 0x07 A : W = value of k8 TABLE ADDWF PCL, 1 RETLW k1 RETLW k2 RETLW kn tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 42 SLEEP Go into standby mode, Clock oscillation stops Syntax SLEEP Operands Operation Status Affected TO, PD OP-Code 00 0000 0000 0011 Description Go into SLEEP mode with the oscillator stopped. Cycle Example SLEEP tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 43 If the content of register 'f' is 0, Zero flag is set to 1. Cycle Example TESTZ REG1 B : REG1 = 0, Z = ? A : REG1 = 0, Z = 1 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 44 W register. If 'd' is 1, the result is stored back in register 'f'. Cycle Example XORWF REG, 1 B : REG = 0xAF, W = 0xB5 A : REG = 0x1A, W = 0xB5 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 45: Electrical Characteristics

    Output current high per all PIN Output current low per 1 PIN Output current low per all PIN +150 Maximum Operating Voltage Operating temperature -40 to +85 °C Storage temperature -65 to +150 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 46: Dc Characteristics

    – – FIRC = 4 MHz = 5V, – – SXT = 32 KHz Slow mode, µA LVR enable, = 3V, – – WKTPSC=11 SXT = 32 KHz = 5V, SIRC – – tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 47 – HYST Low Voltage µs – – Detection time = 0 V = 5V – – KΩ Ports A/B = 3V Pull-Up Resistor = 0 V = 5V – – KΩ = 3V tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 48: Clock Timing

    = 5V, WKTPSC = 00 – – WDT wakeup time = 3V, WKTPSC = 00 – – CPU start up time = 5V – – 6. Characteristic Graphs WDT/WKT TimeOut vs. Voltage -40℃ 0℃ 25℃ 50℃ 85℃ tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 49 UM-TM57PE10_E Advance Information 8-Bit Microcontroller WDT/WKT TimeOut vs. Temperature 2.5V 5.5V ℃ LVR vs. Temperature LV 2.3V LV 1.5V ℃ FIRC Freq vs. Voltage -40℃ 0℃ 25℃ 50℃ 85℃ tenx technology inc. Preliminary Rev 1.4, 2012/01/19...
  • Page 50 UM-TM57PE10_E Advance Information 8-Bit Microcontroller FIRC Freq vs. Temperature 2.5V 3.0V 4.0V 5.0V 5.5V ℃ tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 51: Packaging Information

    SOP 16-pin (150 mil) TM57PE10-OTP-04-X DIP 18-pin (300 mil) TM57PE10-OTP-20-X SOP 18-pin (300 mil) Note: “-X” represents the package material: Package material: Pb-free Code: W  Package material: Green Package Code: G  tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 52: 14-Dip Package Dimension

    8.75 0.337 8.55 0.344 3.80 4.00 0.150 0.157 1.22 1.27 1.32 0.050 0.052 0.048 5.80 6.20 0.228 0.244 0.40 1.27 0.016 0.050 0.10 0.004 0 ° 8 ° 0 ° 8 ° θ tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 53: 16-Dip Package Dimension

    UM-TM57PE10_E Advance Information 8-Bit Microcontroller 16-DIP Package Dimension tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 54: 16-Sop Package Dimension

    UM-TM57PE10_E Advance Information 8-Bit Microcontroller 16-SOP Package Dimension tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

  • Page 55: 18-Dip Package Dimension

    0.125 3.18 8.38 9.65 0.330 0.380 18-SOP Package Dimension (TOP11.55±0.05) (BTM11.60±0.05) 0.508 x 45° 0.762 ± 0.076 15 ° ± 5 ° 1.27 ±0.10 Title SOP 18L Package Outline Drawing Unit 1.27 0.406 tenx technology inc. Preliminary Rev 1.4, 2012/01/19...

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