Philips 47PFL5403 Service Manual page 64

Circuit Diagrams and PWB Layouts
SSB: FPGA I/O Banks
1 2 3
FPGA I/O BANKS
B04D
A
B
+3V3_SW 5700 F701
30R
2701 2702
1u0
10n
+2V5_SW
5701 F702
C 30R
2706 2707 2708 2709 2710 2711
4u7 10n 10n 10n 10n 10n
5702 F703
30R
2717 2718 2719 2720 2721
4u7 10n 10n 10n 10n
D
+1V2_SW
5703
30R
2724 2725 2726
47u 10n 10n
4V
E
5704 5705
F704
30R 30R
F705
2729 2730
1u0 10n
F
G
7700-2
EP2C5F256C7N
Φ
BANK1
ASDO C3
IO_C3|ASDO
nCSO F4 IO_E3|LVDS7 p E3
IO_F4|CSO_
P1
FPGA_BL_BOOST IO_P1|LVDS0 p IO_E4|LVDS7 n
MAIN_SDA P2
IO_P2|LVDS0 n IO_D5|LVDS8 p
N1
IO_N1|LVDS1 p IO_E5|LVDS8 n
AMBI_SDA N2
IO_N2|LVDS1 n IO_C1|LVDS9 p
L1
IO_L1|LVDS2 p IO_C2|LVDS9 n
L2
IO_L2|LVDS2 n IO_L4|PLL1_OUTp
K4
H
FPGA_BL_DIMMING IO_K4|LVDS3 p IO_M4|PLL1_OUTn
K5
IO_K5|LVDS3 n IO_F3|VREFB1N0
K1
IO_K1|LVDS4 n IO_J4|VREFB1N1
K2
IO_K2|LVDS4 p
ambi_pwm(5) E1
IO_E1|LVDS5 p
E2
IO_E2|LVDS5 n
ambi_pwm(2) I728 D3
IO_D3|LVDS6 p
I713 D4
ambi_pwm(3)
IO_D4|LVDS6 n
RES
2700
1n0
I
J
K
L
3139 123 6349.1
1 2 3
LC8.2A LA
4 5 6 7
3747
TxFPGAo_3p
+3V3_FPGA
22R
3748
180R
3749
2703 2704 2705 TxFPGAo_3n
10n 10n 10n
22R
3738
TxFPGAo_1p
22R
3739
180R
3740
TxFPGAo_1n
+2V5out-FPGA
22R
3735
TxFPGAo_0p
22R
2712 2713 2714 2715 3736
10n 180R
10n 10n 10n
3737
TxFPGAo_0n
22R
3741
TxFPGAo_2p
+2V5in-FPGA
22R
3742
180R
3743
TxFPGAo_2n
22R
3744
TxFPGAo_4p
22R
3745
180R
3746
TxFPGAo_4n
+1V2-FPGA
22R
+1V2-PLL
3750
TxFPGAo_CLKp 22R
TxFPGAo_CLKn 3751 22R
3752
TxFPGAe_CLKp 22R
TxFPGAe_CLKn 3753 22R
E4 NC
D5 I712
ambi_pwm(4)
E5
C1 I705
ambi_pwm(0)
C2
ambi_pwm(1)
L4
M4
F3
J4 NC
L3
IO_L3
M1
IO_M1
M2
IO_M2
M3
IO_M3
P3 AMBI_SCL
IO_P3
4 5 6 7
7. 64
8 9 10 11
3720
TxFPGAe_3p
22R
3721
180R
3722
TxFPGAe_3n
22R
INPUT BANK 3723
TxFPGAe_2p
7700-5
22R
EP2C5F256C7N 3724
180R
Φ
3725
TxFPGAe_2n
BANK4
22R
M11 T7
IO_M11|LVDS43p IO_T7|LVDS54p
L11 R7
IO_L11|LVDS43n IO_R7|LVDS54n
3726
T14 T5 TxFPGAe_1p
IO_T14|LVDS44p IO_T5|LVDS55p
R14 R5
IO_R14|LVDS44n IO_R5|LVDS55n 22R
T13 T4 3727
IO_T13|LVDS45p IO_T4|LVDS56p
R13 R4 180R
IO_R13|LVDS45n IO_R4|LVDS56n 3728
TxFPGAe_1n
T12 P5
IO_T12|LVDS46p IO_P5|LVDS57p
R12 P4
22R
IO_R12|LVDS46n IO_P4|LVDS57n
P12 T3
IO_P12|LVDS47p IO_T3|LVDS58p
P13 R3
IO_P13|LVDS47n IO_R3|LVDS58n 3729
K11 N9 TxFPGAe_0p
IO_K11|LVDS48p IO_N9|LVDS59p
K10 N10
IO_K10|LVDS48n IO_N10|LVDS59n 22R
R10 L7 3730
IO_R10|LVDS49p IO_L7|LVDS60p
180R
T10 L8
IO_T10|LVDS49n IO_L8|LVDS60n
3731
L9 N11 TxFPGAe_0n
IO_L9|LVDS50p IO_N11|VREFB4N0
L10 N8
IO_L10|LVDS50n IO_N8|VREFB4N1 22R
T11 L12
IO_T11|LVDS51p IO_L12
R11 P11
IO_R11|LVDS51n IO_P11
T9 T6
IO_T9|LVDS52p IO_T6
R9
IO_R9|LVDS52n
T8
IO_T8|LVDS53p
R8
IO_R8|LVDS53n
3732
TxFPGAe_4p
22R
3733
180R
3734
TxFPGAe_4n
22R
+3V3_FPGA +3V3_FPGA
7700-1
3703 3700 3701 4700
EP2C5F256C7N
10K 10K 10K
Φ
CLK_OSC1
CONTROL
MAIN_SCL H2 G5
0 CE
F706
H1 M13
1 STATUS
J2
2
NC J1 J5
F734
3 CONFIG
H16 L13 I729
CLK I730
4 CONF_DONE
H15
5
J15 J13
6 0
J16 MSEL K12 F733
7 1
F2 TCK_FPGA
TCK
F1 G1 TMS_FPGA
DATA0 TMS
4701
H4 G2 TDO_FPGA
3702
DCLK TDO
DATA0 H5 TDI_FPGA RES
10K
TDI
DCLK
RES
2734
1n0
OUTPUT BANK
EP2C5F256C7N
C4
IO_C4|LVDS10p
C5
IO_C5|LVDS10n
G7
IO_G7|LVDS11p
G6
IO_G6|LVDS11n
F9
IO_F9|LVDS12p
F10 IO_F10|LVDS12n
E6
IO_E6|LVDS13p
F6
IO_F6|LVDS13n
A3
IO_A3|LVDS14p
B3
IO_B3|LVDS14n
A4
NC
IO_A4|LVDS15p
B4
IO_B4|LVDS15n
A5
IO_A5|LVDS16p
B5
IO_B5|LVDS16n
C6
IO_C6|LVDS17p
D6
IO_D6|LVDS17n
A6
IO_A6|LVDS18p
B6
IO_B6|LVDS18n
F8
IO_F8|LVDS19p
F7
IO_F7|LVDS19n
B7
IO_B7|LVDS20p
A7
IO_A7|LVDS20n
8 9 10 11
12 13 14 15
7700-6
EP2C5F256C7N
Φ
+3V3_FPGA
POWER
B1
G3
K3
VCCIO1
R1
+2V5out-FPGA
A15
A2
C10
C7 VCCIO2
E10
E7
B16
G14
K14 VCCIO3
R16
+2V5in-FPGA
M10
M7
P10
P7
VCCIO4
T15
T2
+1V2-FPGA
G9
H10
H7 VCCINT
J7
+1V2-PLL
M5
1
E12
VCCA_PLL
2
L6
1
F11 VCCD_PLL
2
7700-3
Φ
BANK2
B9
7700-4
IO_B9|LVDS21p
A9 EP2C5F256C7N
IO_A9|LVDS21n
D10
Φ
IO_D10|LVDS22p
D11
IO_D11|LVDS22n
BANK3
A10
IO_A10|LVDS23p
B10 D13 M16
IO_B10|LVDS23n IO_D13|LVDS29p IO_M16|LVDS38p
G11 C14 M15
IO_G11|LVDS24p IO_C14|LVDS29n IO_M15|LVDS38n
G10 D16 N16
IO_G10|LVDS24n IO_D16|LVDS30p IO_N16|LVDS39p
A12 D15 N15
IO_A12|LVDS25p IO_D15|LVDS30n IO_N15|LVDS39n
B12 G13 P16
IO_B12|LVDS25n IO_G13|LVDS31p IO_P16|LVDS40p
A13 G12 P15
IO_A13|LVDS26p NC IO_G12|LVDS31n IO_P15|LVDS40n
B13 H11 N14
IO_B13|LVDS26n IO_H11|LVDS32p IO_N14|LVDS41p
C12 J11 N13
IO_C12|LVDS27p IO_J11|LVDS32n IO_N13|LVDS41n NC
C13 NC F16 M12 NC
IO_C13|LVDS27n IO_F16|LVDS33p IO_M12|LVDS42p
A14 F15 N12
IO_A14|LVDS28p IO_F15|LVDS33n IO_N12|LVDS42n
B14 G15 M14
IO_B14|LVDS28n IO_G15|LVDS34p IO_M14|VREFB3N1
D8 G16 H13
IO_D8|VREFB2N1 IO_G16|LVDS34n IO_H13|VREFB3N0
C11 J12 E14
IO_C11|VREFB2N0 IO_J12|LVDS35p IO_E14|PLL2_OUTp
A8 H12 D14
IO_A8 IO_H12|LVDS35n IO_D14|PLL2_OUTn
A11 K15 E16
IO_A11 IO_K15|LVDS36p IO_E16
B11 K16 L14
IO_B11 IO_K16|LVDS36n IO_L14
L16 P14
IO_L16|LVDS37p IO_P14
L15
IO_L15|LVDS37n
12 13 14 15
16 17
2700 I2
2701 B2
2702 B4
B04D
2703 B4
2704 B5
2705 B5
2706 C2
2707 C3
A
2708 C3
2709 C3
2710 C4
2711 C4
2712 C4
2713 C5
2714 C5
2715 C5
2717 D2
2718 D3
2719 D3
2720 D3
B
2721 D4
2724 E3
2725 E3
2726 E4
2729 F3
2730 F3
2734 H8
3700 F10
3701 F11
3702 G11
3703 F10
C 3713 G7
3714 G7
3720 B11
3721 B11
3722 B11
3723 C11
3724 C11
3725 C11
3726 C11
3727 C11
3728 D11
3729 D11
D
3730 D11
3731 D11
3732 E11
3733 E11
3734 E11
3735 C7
3736 C7
3737 C7
3738 B7
3739 C7
3740 C7
A1 3741 D7
E
A16 3742 D7
B15
3743 D7
B2
3744 D7
C8
3745 D7
C9
GND
3746 D7
E8
E9 3747 B7
G8 3748 B7
H14
3749 B7
H3
3750 G7
H8
3751 G7
H9
J14 3752 G7
GND
J3
F 3753 G7
J8
4700 F11
J9
4701 G11
K9
5700 B2
M8
M9 5701 C2
P8
5702 D2
P9
5703 D2
GND R15
5704 E2
R2
5705 E3
T1
T16 7700-1 F9
7700-2 G4
L5
7700-3 H12
GND_PLL1 N5 G
7700-4 I14
D12 7700-5 C9
GND_PLL2 F12 7700-6 E15
7700-7 I16
M6
F701 B2
1
E11
GNDA_PLL
2 F702 C2
F703 D2
F704 E3
F705 F2
F706 G10
F733 G10
F734 G10
H
I705 H5
I712 H5
I713 H3
I728 H3
I729 G10
I730 G11
7700-7 I
EP2C5F256C7N
Φ
NC
B8 H6
C15 J10
C16 J6
D1 K13
D2 K6
D7 K7
D9 K8
NC
NC NC
E13 N3
E15 N4
F13 N6 J
F14 N7
F5 P6
G4 R6
K
L
I_17760_008.eps
180208
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