Philips 40PFL7664H/12 Service Manual page 18

EN 18 5. Q548.1E LB
Detect2 should be polled on the standard 40ms
interval and startup should be continued when
detect2 becomes high.
This enables the +3V3 and +5V converter. As a
result, also +5V-tuner, +2V5, +1V8-PNX8541 and
+1V8-PNX5100 (if present) become available.
No
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2009-Dec-18
Service Modes, Error Codes, and Fault Finding
Standby Supply starts running.
All standby supply voltages become available.
Initialise I/O pins of the st-by µP:
- Switch reset-AVC LOW (reset state)
- Switch WP-NandFlash LOW (protected)
- Switch reset-system LOW (reset state)
- Switch reset-5100 LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- keep reset-NVM high, Audio-reset and Audio-Mute-Up HIGH
start keyboard scanning, RC detection. Wake up reasons are
Reset detect2_delay_flag
Switch ON Platform and display supply by switching
LOW the Standby line.
+12V, +24Vs, AL and Bolt-on power
is switched on, followed by the +1V2 DCDC converter
Delay 1.5 second before checking detect2 line
if the detect2_delay_flag is set
Detect2 high received
No
Wait fixed time of 15ms
Reset detect2_delay_flag
Enable the DCDC converter for +3V3 and
+5V. (ENABLE-3V3)
Delay of 50ms needed because of the latency of
the detect-1 circuit. This delay is also needed for
the PNX5100. The reset of the PNX5100 should
only be released 10ms after powering the IC.
Enable the supply detection algorithm
Set I²C slave address
of Standby µP to (A0h)
Switch LOW the RESET-NVM line to allow access to NVM. (Add a
2ms delay before trying to address the NVM to allow correct NVM
initialization, this is no issue in this setup, the delay is automatically
covered by the architectural setup)
Switch HIGH the WP-NandFlash to
allow access to NAND Flash
Release Reset-PNX5100.
PNX5100 will start booting.
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
No
Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script
Figure 5-4 "Off/Stand-by" to "Semi Stand-by" flowchart (part 1)
Off
Stand by or
Mains is applied
Protection
st-by µP resets
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.
- Switch Audio-Reset high.
It is low in the standby mode if the standby
mode lasted longer than 10s.
off.
Carefull we don't hit this error
directly if the delay flag is set.
Power-OK error:
No Layer1: 3
within 2 seconds?
Layer2: 16
Yes
Enter protection
If the supply is hicking, the first detect2 could
be positive (12V still present), followed by
negative Supply-fault (already low). Adding a
Detect2 high?
fixed delay brings us behind this delay gap.
Yes
Wait 50ms
Detect-1 I/O line Detect-2 I/O line
No
High? High?
Yes
Wait 50ms
Yes
Detect-1 I/O line
Yes
High?
No
Detect-2 I/O line
High?
Yes
Voltage output error:
Layer1: 2
Layer2: 18
Only usefull in case of PNX5100 present. To avoid
diversity in standby µP, the reset-PNX5100 will still be
switched by the standby µP.
This 10ms delay is still present to give some relaxation
Wait 10 ms to the supplies. (The PCI arbiter on the PNX5100 is
never used and is not the reason anymore)
An EJTAG probe (e.g. WindPower ICE probe) can be
connected for Linux Kernel debugging purposes.
EJTAG probe
Yes
connected ?
No
Cold boot?
Yes
Release AVC system reset
Feed initializing boot script
disable alive mechanism
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Confirmation received from NXP that there does not need to
be a delay between the rise of the +1V2 and the +3V3. Only
requirement is to have the +1V2 before or at the same time
as the +3V3. 150ms delay is deleted.
Set detect2_delay_flag
Disable 3V3, switch standby
No
line high and wait 4 seconds
These checks prevent the set from going in to
standby on the false error condition where the
first 3V3 is negative because of a hickup,
although the 12V was about to reappear.
Because of this reappearance, the 12V check
is OK which would cause protection. If we wait
50ms, the 3V3 should be back as well.
No
Enter protection
This will allow access to NVM and
NAND FLASH and can not be done
earlier because the FLASH needs to
be in Write Protect as long as the
supplies are not available.
18440_216a_090227.eps
091118