IBASE Technology IB905 User Manual page 28

Intel sandy bridge / pch 3.5-inch embedded board
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BIOS SETUP
PCI Subsystem Settings
This section allows you to configure the PCI, PCI-X and PCI Express
settings.
Advanced
Main
PCI Bus Driver Version
PCI ROM Priority
PCI Common Settings
PCI Latency Timer
VGA Palette Snoop
PERR# Generation
SERR# Generation
PCI Express Device Settings
Relaxed Ordering
Extended Tag
No Snoop
Maximum Payload
Maximum Read Request
PCI Express Link Settings
ASPM Support
WARNING: Enabling ASPM may cause some
PCI-E devices to fail
Extended Synch
PCI ROM Priority
In case of multiple Option ROMs (Legacy and EFI Compatible), specifies
what PCI Option ROM to launch.
PCI Latency Timer
Value to be programmed into PCI Latency Timer Register.
VGA Palette Snoop
Enables or Disables VGA Palette Registers Snooping.
PERR# Generation
Enables or Disables PCI Device to Generate PERR#.
SERR# Generation
Enables or Disables PCI Device to Generate SERR#.
Relaxed Ordering
Enables or Disables PCI Express Device Relaxed Ordering.
24
Aptio Setup Utility
Chipset
Boot
V 2.03.00
EFI Compatible ROM
32 PCI Bus Clocks
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Auto
Auto
Disabled
Disabled
IB905 User's Manual
Security
Save & Exit
→ ←
Select Screen
↑↓ Select Item
Enter: Select
+-
Change Field
F1: General Help
F2: Previous Values
F3: Optimized Default
F4: Save & Exit
ESC: Exit

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