Spectravideo SVI 318 Service – Technical Manual page 71

Mach ine Cyc l e One ( output , act ive Low) .
MI
MREQ , indicates that tbe cur rent mach i ne
fetch cyc l e of an inst ruct i on execut ion .
Memory Request ( ou tput , act ive Lo w , 3 - s t ate ) .
MREQ
that the addre s s bus ho l d s a va l i d address for a memory read
or memory wr i te operat ion .
Non-Maskab l e Int e r r u f!_ ( inpu t , ac t i ve Low) .
NMI
p r i or i t y than INT .
the current ins t r uc t i on , independent o f the s ta t us of the
interrupt enab l e f l ip-f l op , and a u toma t ica l ly f orces the CPU
to re s t a r t at loca t ion 0066 H .
RD Memory Read ( ou tp u t , ac t ive Low , 3-state ) .
the CPU wan t s to read data f rom memory or an 1 /0 device .
add re ssed I / 0 dev i ce or memory sho u l d use th i s s i gna l to
9ata on to t he CPU data b us .
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RE SET Re set ( inpu t , a c t i ve Low) .
fo l lows :
It re se t s the interrup t enab l e f l ip-f l op , c l e a r s the PC and
Reg i s te r s I and R , and s e t s t he int errupt s ta t us to Mode 0 .
Dur i ng re set t i me , the addre s s and data bus go to a h igh­
impendance sta t e , and a l l cont r o l ou tput s igna l s go to the
ina c t i ve s t a t e .
min imum o f three fu l l c l ock cyc l e s be fore the re s e t ope ra t i on
i s comp l e te d .
RFSH Re f r e sh ( output , a c t ive Low) .
ind i ca t e s that the lower seven b i t s of the system ' s address
b us can be used as a re f re sh a dd r e ss to the s y s t em ' s dynam ic
memo r i e s .
WA IT
Wai t ( input , ac t i ve Low) .
a dd re s se d memory or I / 0 devices a re not ready for a data
t ra ns f e r .
th i s s i gna l i s ac t ive .
CPU f rom re f re sh ing dynam ic memory p roper l y .
Memory Wr i te ( ou t pu t , act ive Low , 3-state ) .
the CPU data bus ho l d s va l id data to be store d at the addre s se d
memory or I /O location .
NMI is a lway s recogn i zed at the end o f
RESET i n i t i a l i z e s t he CPU a s
N o te that RESET must be act i ve f or a
WAIT indica tes to the CPU tha t the
The CPU cont i nues to enter a Wa i t s t a te as long as
Extended WAIT periods can p revent the
4 . 3B
c � l e i s the opcode
Ml , together with
cyc l e .
MREQ indicates
NMI has a h ighe r
RD indicates
RFSH , toge ther w i th MREQ ,
WR indicates that
tha t
The
gate