Pin Descriptions - Spectravideo SVI 318 Service – Technical Manual

P IN DESCRIPTIONS
Add re s s Bus ( ou tp u t ,
1 6 -b i t a dd r e s s b u s .
memo ry d a t a bus e x c hange s ( up to
e x chang e s .
Bus Acknow l e dg e ( ou t p u t ,
BUSACK
in d i c a t e s t o t he re que s t i n g
d a t a bus , and co n t r o l s i g na l s
e nt e re d t h e i r h i gh- impe d a n c e
c a n now con t r o l the s e l i ne s .
BUSREQ
Bus Re que s t ( in p u t , ac t i ve L ow ) .
p r i o r i t y than NMI and is a l wa ¥ recogn i z e d a t the end o f the
cu r r e n t mach i ne c yc l e .
d a t a bus , and co n t ro l s i g na l s
to a h i gh- impe dance s t a t e so th a t o t h e r dev i c e s can con t r o l
t he se l in e s .
. e x t e rna l pu l l up for the s e app 1 i c a t ion s .
p e r i o d s due to e x t e n s i ve DMA ope r a t i on s can p r event the CPU
f rom p rope r ly re f re s h ing dy nam i c RAM s .
Da ta Bus ( i nput / ou t pu t , ac t i ve H i gh , 3 - s t a t e ) .
cons t i t u t e an 8-b i t b i d i re c t i ona l data bus , use d for data
exchan g e s w i th memory and I / O .
HALT
H a l t S t a te ( ou t p u t , a c t i ve Low ) .
h a s e x ec u t e d a Ha l t in s t r uc t i o n and is awa i t i n g e i t he r a non­
maskab l e or a ma skab l e i n t e r r u p t ( w i th t he ma s k e nab l e d ) b e f o r e
ope r a t i o n can re s ume .
ma i n t a in memory re f r e sh .
!NT
In t e r r up t Reque s t ( i npu t , ac t ive Low ) .
gene r a t e d b y I / 0 dev i c e s .
end of the c u r r e n t i n s t ruc t ion if th e i n t e rn a l s o f tware­
cont ro l l e d i n t e r r u p t enab l e f l ip - f l o p ( I FF ) is e nab l e d .
is norma l ly w i re-OR e d and re qu i r e s an e x t e rn a l pu l l up for the s e
app l i c a t i ons .
I ORQ
Inpu t / Ou t pu t Re que s t ( ou t pu t , a c t i ve ·Low , 3 - s t a t e ) .
indicat e s that t he l ow e r ha l f o f t he a ddre s s b u s h o l d s a va l i d
1 / 0 a dd re s s fo r a n I / O rea d o r w r i t e op e r a t i on .
gene ra te d concu r r e n t ly w i th M l du r i dng an i n t errupt acknow l e dge
cy c l e t o ind i ca t e t h a t an i n t e r r up t re s p o n s e ve c t o r can be
p l ace d on t he da t a b us .
ac t i v e H i gh , 3 -
The A dd r e s s Bus p r o v i d e s
L ow ) .
ac t i v e
de v i ce t h a t the
a
s t
MREQ , I ORQ ,
t
BUSREQ f o r c e s t he CPU a dd r e s s bus ,
MREQ ,
BUSREQ i s n o rma l l y w i re-ORed and r e qu i re s an
Wh i l e ha l t e d , t h e CPU execu t e s NOP
The CPU honors a r e qu e s t a t the
4 . 37
e ) .
s a t A0- A15
t
s
a dd r e s s f o r
y
t he
b ) and f o r 1 / 0 d e v i c e
6 4 K t e
Bus Acknow l e dge
a d d r e s s b u s ,
C P U
e x r a
and WR have
.
s t n c i r cu i t ry
e The e l
Bus Requ e s t a h ighe r
ha s
I ORQ , RD , and WR to go
E x t e n d e d BU SREQ
D� -
HALT i n d i c a t e s that t he CPU
In t e r rupt R e qu e s t i s
I ORQ i s a l s o
form a
D 7
t o
! NT
I ORQ