Siemens A70 Service Repair Documentation page 39

Company Confidential
Copyright 2005© Siemens AG
Functions Pin Requirements Implementation/Sequence
Voltage Supply VLPREG
RTC
Voltage Supply VREGSIM
SIM
Charge Support CHARGE_UC,
CHARGE,
VDDCHARGE,
AVDD, SENSE_IN,
TBAT
Voltage
supervision
Supervision of REG1
REG1 and REG2
REG2
Powersupply VDD
supervision
VDDA VDDA
supervision
TD_Repair_L2.5_A70_A75_R1.0.pdf
The linear controller is designed for 2.00V(min. 1.9V, max.
2.1V) and a maximum load current of 1 mA.
The output voltage can be adjusted to four different values
with TWI register by the µC. The selectable values are
2.00(default), 1.82, 1.92 and 2.07V. LP-LDO is always
working and will switch of only with POR signal.
The linear controller is designed for 2.9V(min. 2.84V, max.
2.96V) and a maximum load current of 60 mA. The output
voltage can be adjusted to a different value with TWI register
by the µC to 1.8V(min. 1.76V, max. 1.84V).
This regulator can be activated by TWI register, but only in
active mode. If the regulator is in power down, the output is
pulled down by a transistor to avoid electrostatic charging of
VREGSIM.
A charge support will be integrated for controlling the battery
charge function. It consists basically of a temperature sensor,
an external charge FET, an integrated High-side driver for the
external FET with an external resistor between the source
and the gate of the charge FET.
In the case of a rising edge at the CHARGE_UP the power
source will be switched on. In this way the charge FET
becomes conducting,
temperature comparator does not give the signal for extreme
temperature and that no overvoltage is present at the VDD. In
the case of falling slope at the CHARGE_UP, the current
source is switched off and the pull-up resistor will make sure
that the charge FET is blocked after a finite time.
Temperature switchoff becomes effective at approx. T>60°C.
The levels of regulator REG1, REG2, REGA, SIM_LDO, and
also the supply voltage
comparators.
In active mode the regulators are supervised permanently. If
the voltage is under the threshold, the pin RESET_N stay Low
and the ASIC go back to the power down mode. If the voltage
is longer than Tmin under threshold voltage, the RESET_N is
going to Low (Missing Watchdog signal -> phone switched
off). The level of regulator REG1 and REG2 will be
supervised permanently. If the voltage doesn't reach the
threshold value at switch on, the RESET_N pin will stay low
and the ASIC will go back to power down mode. The voltages
are sensed continuously and digitally filtered with a time
constant Tmin. If the regulator voltage is under threshold
longer than Tmin, the RESET_N signal change to low and the
uC will go to RESET condition (Missing Watchdog signal ->
phone switched off).
If the battery voltage VDD exceeds VDD_high everything is
switched off immediately within 1µs. Only the pullup circuitry
for the external charge PMOS are active and will discharge
the gate of the external PMOS
To provide a short circuit protection at output of VDDA and
output of stereo buffer a voltage supervision is implemented.
If the VDDA output is less then this threshold, the VDDA will
be switched off for 128ms. After this time the VDDA will be
started again. The VDDA supervision starts 60ms after
startup of VDDA.
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s Com
provided that the
VBAT are supervised
integrated
with
Release 1.0